CHA2063A_15 Datasheet, PDF (9/10 Pages) United Monolithic Semiconductors – 7-13GHz Low Noise Amplifier

7-13GHz Low Noise Amplifier
Typical Chip Assembly
Vd
C = 100pF
CHA2063a
IN
OUT
Chip Biasing options
This chip is self-biased, and flexibility is provided by the access to number of pads. the
internal DC electrical schematic is given in order to use these pads in a safe way.
G1
2k
Vd
55
G2
55
2k
21
21
31
1k
1k
A
B
C
21
21
E
D
The two requirements are :
N°1 : Not exceed Vds = 3.5Volt (internal Drain to S ource voltage).
N°2 : Biased in such a way to limit Vgs positive va lue (internal Gate to Source voltage).
We propose two standard biasing :
Low Noise and low consumption :
Vd = 4V and B & D grounded.
All the other pads non connected ( NC ).
Idd = 40mA & Pout-1dB = +8dBm Typical.
( Equivalent to A,B,C,D,E : NC and Vd=4V ; G1=+2.5V ; G2=+2.5V).
Low Noise and high output power :
Vd = 5V and B & E grounded.
All the other pads non connected ( NC ).
Idd = 75mA & Pout-1dB = +13dBm Typical.
( Equivalent to A,B,C,D,E : NC and Vd=5V ; G1=+2.5V ; G2=+1.0V).
Ref. : DSCHA20630096 -05-Apr-00
9/10
Specifications subject to change without notice
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