C0402C0G1C010C020BC Datasheet, PDF (4/35 Pages) TDK Electronics – Commercial Grade ( General (Up to 50V) )

BR25G128-3
Datasheet
AC Characteristics (Ta=-40°C to +85°C, unless otherwise specified, load capacity C_L=30pF)
Parameter
Symbol
1.6≤Vcc<1.7V 1.7≤Vcc<2.5V 2.5≤Vcc<4.5V 4.5≤Vcc≤5.5V Unit
Min Typ Max Min Typ Max Min Typ Max Min Typ Max .
SCK Frequency
f_SCK 0.01 - 3 0.01 - 5 0.01 - 10 0.01 - 20 MHz
SCK High Time
t_SCKWH 125 - - 80 - - 40 - - 20 - - ns
SCK Low Time
t_SCKWL 125 - - 80 - - 40 - - 20 - - ns
CSB High Time
t_CS 200 - - 90 - - 40 - - 20 - - ns
CSB Setup Time
t_CSS 100 - - 60 - - 30 - - 15 - - ns
CSB Hold Time
t_CSH 100 - - 60 - - 30 - - 15 - - ns
SCK Setup Time
t_SCKS 100 - - 50 - - 20 - - 15 - - ns
SCK Hold Time
t_SCKH 100 - - 50 - - 20 - - 15 - - ns
SI Setup Time
t_DIS 30 - - 20 - - 10 - - 5 - - ns
SI Hold Time
t_DIH 50 - - 20 - - 10 - - 5 - - ns
Data Output Delay Time
t_PD
- - 125 - - 70 - - 40 - - 20 ns
Output Hold Time
t_OH
0 - - 0 - - 0 - - 0 - - ns
Output Disable Time
t_OZ
- - 200 - - 80 - - 40 - - 20 ns
HOLDB Setting Setup Time
t_HFS
0 - - 0 - - 0 - - 0 - - ns
HOLDB Setting Hold Time
t_HFH 100 - - 20 - - 10 - - 5 - - ns
HOLDB Release Setup Time
t_HRS
0 - - 0 - - 0 - - 0 - - ns
HOLDB Release Hold Time
t_HRH 100 - - 20 - - 10 - - 5 - - ns
Time from HOLDB to Output High-Z
t_HOZ
- - 100 - - 80 - - 40 - - 20 ns
Time from HOLDB to Output change
SCK Rise Time ^(Note1)
SCK Fall Time ^(Note1)
OUTPUT Rise Time ^(Note1)
OUTPUT Fall Time ^(Note1)
t_HPD
- - 100 - - 80 - - 40 - - 20 ns
t_RC
- - 2 - - 2 - - 2 - - 2 µs
t_FC
- - 2 - - 2 - - 2 - - 2 µs
t_RO
- - 100 - - 50 - - 40 - - 20 ns
t_FO
- - 100 - - 50 - - 40 - - 20 ns
Write Cycle Time
t_E/W
- - 5 - - 5 - - 5 - - 5 ms
(Note1) NOT 100% TESTED
AC Timing Characteristics Conditions
Parameter
Symbol
Min
Limits
Typ
Max
Unit
Load Capacity
C_L
-
-
30
pF
Input Voltage
-
0.2Vcc/0.8Vcc
V
Input / Output Judgment Voltage
-
0.3Vcc/0.7Vcc
V
Input / output capacity (Ta=25°C, frequency=5MHz)
Parameter
Symbol Min Max Unit
Input Capacity ^(Note1)
Output Capacity ^(Note1)
C_IN
－
8
pF
C_OUT
－
8
(Note1) NOT 100% TESTED
Conditions
V_IN=GND
V_OUT=GND
Serial Input / Output Timing
CSB
SCK
tCS
tSCKS
tCSS
SI
SO
tSCKWL tSCKWH
tDIS tDIH
tRC
tFC
High-Z
Figure 2-(a). Input timing
SI is taken into IC inside in sync with data rise edge of
SCK. Input address and data from the most significant bit
MSB
"H"
CSB
"L"
SCK
tHFS tHFH
SI
n+1
SO
Dn+1
tHOZ
Dn
tHRS tHRH
High-Z
tDIS
n
tHPD
Dn
n-1
Dn-1
HOLDB
Figure 2-(c). HOLD timing
tCS
CSB
SCK
SI
SO
tPD
tOH
tCSH ^tSCKH
tRO,tFO tOZ
High-Z
Figure 2-(b). Input / Output timing
SO is output in sync with data fall edge of SCK. Data is
output from the most significant bit MSB.
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TSZ02201-0R2R0G100670-1-2
19.Mar.2014 Rev.001