C0402C0G1C010C020BC Datasheet, PDF (14/35 Pages) TDK Electronics – Commercial Grade ( General (Up to 50V) )

BR25G128-3
Datasheet
Features
1. Status Registers
This IC has status register. The status register expresses the following parameters of 8 bits.
BP0 and BP1 can be set by write status register command. These 2 bits are memorized into the EEPROM, therefore are
valid even when power source is turned off.
Rewrite characteristics and data hold time are same as characteristics of the EEPROM.
WEN can be set by write enable command and write disable command. WEN becomes write disable status when power
source is turned off. R/B is for write confirmation, therefore cannot be set externally.
The value of status register can be read by read status register command.
(1) Contexture of Status Register
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
WPEN
0
0
0
BP1
BP0 WEN
―
R/B
bit
Memory
location
WPEN EEPROM
Function
WPB pin enable / disable designation bit
WPEN=0=invalid
WPEN=1=valid
BP1
BP0
WEN
EEPROM
registers
―
R/B
registers
EEPROM write disable block designation bit
Write and write status register write enable / disable status confirmation bit
WEN=0=prohibited
WEN=1=permitted
Write cycle status (READY / BUSY) status confirmation bit
―
R/B=0=READY
―
R/B=1=BUSY
(2) Write Disable Block Setting
BP1
BP0
Write disable block
0
0
None
0
1
3000h-3FFFh
1
0
2000h-3FFFh
1
1
0000h-3FFFh
2. WPB Pin
By setting WPB=LOW, write command is prohibited. And the write command to be disabled at this moment is WRSR.
However, when write cycle is in execution, no interruption can be made.
WRSR
WRITE
Prohibition possible
but WPEN bit “1”
Prohibition
impossible
3. HOLDB Pin
By HOLDB pin, data transfer can be interrupted. When SCK=”0”, by making HOLDB from “1” into”0”, data transfer to
EEPROM is interrupted. When SCK = “0”, by making HOLDB from “0” into “1”, data transfer is restarted.
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TSZ02201-0R2R0G100670-1-2
19.Mar.2014 Rev.001