TMP89FS60 Datasheet, PDF (89/410 Pages) Toshiba Semiconductor – 8 Bit Microcontroller

TMP89FS60
Watchdog timer status
WDST
7
6
5
4
3
2
1
0
(0x0FD7)
Bit Symbol
-
-
-
-
-
WINTST2 WINTST1 WDTST
Read/Write
R
R
R
R
R
R
R
R
After reset
0
1
0
1
1
0
0
1
Watchdog timer interrupt request
WINTST2
signal factor status 2
Watchdog timer interrupt request
WINTST1
signal factor status 1
WDTST
Watchdog timer operating state sta-
tus
0 : No watchdog timer interrupt request signal has occurred.
1 : A watchdog timer interrupt request signal has occurred due to the over-
flow of the 8-bit up counter.
0 : No watchdog timer interrupt request signal has occurred.
1 : A watchdog timer interrupt request signal has occurred due to releasing of
the 8-bit up counter outside the clear time.
0 : Operation disabled
1 : Operation enabled
Note 1: WDST<WINTST2> and WDST<WINTST1> are cleared to "0" by reading WDST.
Note 2: Values after reset are read from bits 7 to 3 of WDST.
5.3 Functions
The watchdog timer can detect the CPU malfunctions and deadlock by detecting the overflow of the 8-bit up
counter and detecting releasing of the 8-bit up counter outside the clear time.
The watchdog timer stoppage and other abnormalities can be detected by reading the count value of the 8-bit up
counter at random times and comparing the value to the last read value.
5.3.1 Setting of enabling/disabling the watchdog timer operation
Setting WDCTR<WDTEN> to "1" enables the watchdog timer operation, and the 8-bit up counter starts
counting the source clock.
WDCTR<WDTEN> is initialized to "1" after the warm-up operation that follows reset is released. This
means that the watchdog timer is enabled.
To disable the watchdog timer operation, clear WDCTR<WDTEN> to "0" and write 0xB1 into WDCDR.
Disabling the watchdog timer operation clears the 8-bit up counter to "0".
Note:If the overflow of the 8-bit up counter occurs at the same time as 0xB1 (disable code) is written into WDCDR
with WDCTR<WDTEN> set at "1", the watchdog timer operation is disabled preferentially and the overflow
detection is not executed.
To re-enable the watchdog timer operation, set WDCTR<WDTEN> to "1". There is no need to write a con-
trol code into WDCDR.
Watchdog timer source clock
8-bit up counter value
00H
01H
FFH
00H
WDCTR<WDTEN>
WDCTR<WDTEN>
Interrupt request signal
1 clock (max.)
Overflow time
Overflow time
RA000
Figure 5-2 WDCTR<WDTEN> Set Timing and Overflow Time
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