TMP89FS60 Datasheet, PDF (50/410 Pages) Toshiba Semiconductor – 8 Bit Microcontroller

2. CPU Core
2.3 System clock controller
TMP89FS60
Example 1: Switching from the NORMAL2 mode to the SLOW1 mode (when fc is used as the basic clock for the high-fre-
quency clock)
SET
(SYSCR2).4
NOP
NOP
CLR
(SYSCR2).6
; SYSCR2<SYSCK> = 1
; (Switches the main system clock to the basic clock for the low-frequen-
cy clock for the SLOW2 mode)
; Waits for 2 machine cycles
; SYSCR2<XEN> = 0
(Turns off the high-frequency clock oscillation circuit)
Example 2: Switching to the SLOW1 mode after the stable oscillation of the low-frequency clock oscillation circuit is con-
firmed at the warm-up counter (fs=32.768KHz, warm-up time = about 100 ms)
PINTWUC:
VINTWUC:
; #### Initialize routine ####
SET
(P0FC).2
; P0FC2 = 1
(Uses P02/03 as oscillators)
¦
¦
LD
(WUCCR), 0x02
; WUCCR<WUCDIV> = 00 (No division)
WUCCR<WUCSEL> = 1 (Selects fs as the source clock)
LD
(WUCDR), 0x33
; Sets the warm-up time
(Determines the time depending on the oscillator characteristics)
100 ms/1.95 ms = 51.2 → round up to 0x33
SET
(EIRL).4
; Enables INTWUC interrupts
SET
(SYSCR2).5
; SYSCR2<XTEN> = 1
(Starts the low-frequency clock oscillation and starts the warm-up
counter)
¦
; #### Interrupt service routine of warm-up counter interrupts ####
SET
(SYSCR2).4
; SYSCR2<SYSCK> = 1
(Switches the main system clock to the low-frequency clock)
NOP
; Waits for 2 machine cycles
NOP
CLR
(SYSCR2).6
; SYSCR2<XEN> = 0 (Turns off the high-frequency clock oscillation cir-
cuit)
RETI
¦
DW
PINTWUC
; INTWUC vector table
RA001
(2) Switching from the SLOW1 mode to the NORMAL1 mode
Set SYSCR2<XEN> to "1" to enable the high-frequency clock (fc) to oscillate. Confirm at the
warm-up counter that the oscillation of the basic clock for the high-frequency clock has stabilized,
and then clear SYSCR2<SYSCK> to "0".
When a maximum of 8/fs + 2.5/fcgck [s] has elapsed since SYSCR2<SYSCK> is cleared to "0",
the main system clock (fm) is switched to fcgck.
After switching, wait for 2 machine cycles or longer, and then clear SYSCR2<XTEN> to "0" to
turn off the low-frequency clock oscillator.
The SLOW mode is also released by a reset by the RESET pin, a power-on reset and a reset by the
voltage detection circuits. When a reset is released, the warm-up starts. After the warm-up is com-
pleted, the NORMAL1 mode becomes active.
Note 1: Be sure to follow this procedure to switch the operation from the SLOW1 mode to the
NORMAL1 mode.
Note 2: After switching SYSCR2<SYSCK>, be sure to wait for 2 machine cycles or longer before clear-
ing SYSCR2<XTEN> to "0". Clearing it within 2 machine cycles causes a system clock reset.
Note 3: When the main system clock (fm) is switched, the gear clock (fcgck) is synchronized with the
clock that is a quarter of the basic clock (fs) for the low-frequency clock. For the synchronization,
fm is stopped for a period of 2.5/fcgck [s] or shorter.
Note 4: When P0FC0 is "0", setting SYSCR2<XEN> to "1" causes a system clock reset.
Note 5: When SYSCR2<XEN> is set at "1", writing "1" to SYSCR2<XEN> does not cause the warm-up
counter to start counting the source clock.
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