TMP19A64C1DXBG Datasheet, PDF (88/460 Pages) Toshiba Semiconductor – 32-bit RISC Microprocessor

TMP19A64C1D
Port 3 register
7
6
5
4
3
2
1
0
P3
Bit Symbol P37
P36
P35
P34
P33
P32
P31
P30
(0xFFFF_F018) Read/Write
R/W
After reset To be
Output mode
determined
according
to the bus
1
1
1
1
1
1
1
mode (*1)
P3CR
(0xFFFF_F01A)
Bit Symbol
Read/Write
After reset
Function
7
P37C
To be
determined
according
to the bus
mode (*1)
Port 3 control register
6
P36C
0
5
4
P35C
P34C
R/W
0
0
3
P33C
0
0: Input
1: Output
2
P32C
0
1
0
⎯
⎯
R
0
0
Output
P3FC
(0xFFFF_F01B)
Bit Symbol
Read/Write
After reset
Function
7
P37F
0
0: PORT
1: ALE
Port 3 function register
6
5
4
3
P36F
0
0: PORT
1: R/W
P35F
0
0: PORT
1:
BUSAK
P34F
P33F
R/W
0
0
0: PORT 0: PORT/
WAIT
1: BUSRQ 1: PORT/
RDY
2
P32F
0
0: PORT
1: HWR
1
P31F
0
P30F
0
0
0: PORT 0: PORT
1: WR
1: RD
Function
RD output setting
WR output setting
HWR output setting
WAIT input setting
RDY input setting
BUSRQ input setting
BUSAK output setting
R/W output setting
ALE output setting (BUSMD = "1")
Corresponding
BIT of P3FC
1(*2)
1(*2)
1
0
1
1
1
1
1(*1)
Corresponding
BIT of P3CR
−
−
1
0
0
0
1
1
1
PORT to be used
P30
P31
P32
P33
P34
P35
P36
P37
(*1)
In separate bus mode (BUSMD="0"), ALE is not output. The port 3 functions as an
input/output port based on the bit setting of the control register P3CR<P37C>. After a reset,
the port becomes an input port. If a reset is executed in multiplexed bus mode
(BUSMD="1"), the port 3 becomes an output port at "L" level.
(*2) /RD and /WR are output only when an external area is being accessed.
Fig. 7.4.6 Port 3 Registers
TMP19A64 (rev1.1) 7-14