TMP19A64C1DXBG Datasheet, PDF (81/460 Pages) Toshiba Semiconductor – 32-bit RISC Microprocessor

TMP19A64C1D
7.4 Port 3 (P30 through P37)
The port 3 is a general-purpose, 8-bit input/output port (P30 and P31 are used exclusively for output). For this
port, inputs and outputs can be specified in units of bits by using the control register P3CR and the function
register P3FC.
A reset allows the output latches P30 and 31 to be set to "1." If the BUSMD pin is at the "L" level when a reset
is performed, P37 goes into separate bus mode, and the output latch is set to "1." If the BUSMD pin is at the "H"
level when a reset is performed, P37 goes into multiplexed bus mode, and the output latch is cleared to "0." Bit 2
through bit 6 of P3CR (bits 0 and 1 are unused) are cleared to "0." Bit 7 of P3CR is cleared to "0" in separate
bus mode and set to "1" in multiplexed bus mode. All bits of P3FC are cleared to "0," P30 and P31 generate "H,"
and P32 through P36 go into the input mode with a pull-up resistor after RESET is cleared. If the port 3 goes
into separate bus mode, P37 is put into input mode. If the port 3 goes into multiplexed bus mode, P37 is put into
output mode.
Besides the general-purpose input/output port function, the port 3 inputs and outputs CPU control/status signals.
If the P30 pin is set to RD signal output mode (<P30F>="1"), the RD strobe is output only when an external
address area is accessed. Likewise, if the P31 pin is set to WR signal output mode (<P31F>="1"), the WR
strobe is output only when an external address area is accessed.
As for P32 and P36, when <P3xFC> ="1," and BUSAK ="0," Pull-up is enabled.
During external access
Function control
(in units of bits)
P3FC
S
0
1
Output latch
S
P3
0
1
P3 write
RD , WR
P3 read
Fig. 7.4.1 Port 3 (P30, P31)
STOP MODE
SYSCR2<DRVE>
P30 ( RD )
P31 ( WR )
TMP19A64 (rev1.1) 7-7