TMP19A64C1DXBG Datasheet, PDF (201/460 Pages) Toshiba Semiconductor – 32-bit RISC Microprocessor

TMP19A64C1D
Bit Mnemonic
Field name
Description
17
Big
Big-endian
Big Endian (initial value: 1)
1: A channel operates by big-endian
0: A channel operates by little-endian
16
⎯
(Reserved)
This is a reserved bit. Always set this bit to "0."
15
⎯
(Reserved)
This is a reserved bit. Always set this bit to "0."
14
ExR
External request mode External Request Mode (initial value: 0)
Selects a transfer request mode.
1: External transfer request (interrupt request or external DREQn request)
0: Internal transfer request (software initiated)
13
PosE Positive edge
Positive Edge (initial value: 0)
The effective level of the transfer request signal INTDREQn or DREQn is
specified. This function is valid only if the transfer request is an external
transfer request (if the ExR bit is 1). If it is an internal transfer request (if
the ExR bit is 0), the PosE value is ignored. Because the INTDREQn and
DREQn signals are active at "L" level, make sure that this PosE bit is set
to "0."
1: Setting prohibited
0: The falling edge of the INTDREQn or DREQn signal or the "L" level is
effective. The DACKn is active at "L" level.
12
Lev
Level mode
Level Mode (initial value: 0)
Specifies which is used to recognize the external transfer request, signal
level or signal change. This setting is valid only if a transfer request is the
external transfer request (if the ExR bit is 1). If the internal transfer
request is specified as a transfer request (if the ExR bit is 0), the value of
the Lev bit is ignored. Because the INTDREQn signal is active at "L"
level, make sure that you set the Lev bit to "1." The state of active DREQn
is determined by the Lev bit setting.
1: Level mode
The level of the DREQn signal is recognized as a data transfer request.
(The "L" level is recognized if the PosE bit is 0.
0: Edge mode
A change in the DREQn signal is recognized as a data transfer request.
(A falling edge is recognized if the PosE bit is 0.)
11
SReq Snoop request
Snoop Request (initial value: 0)
The use of the snoop function is specified by asserting the bus control
request mode. If the snoop function is used, the snoop function of the
TX19A processor core is enabled and the DMAC can use the data bus of
the TX19A processor core. If the snoop function is not used, the snoop
function of the TX19A processor core does not work.
1: Use snoop function (SREQ)
0: Do not use snoop function (GREQ)
10
RelEn Bus control release Release Request Enable (initial value: 0)
request enable
Acknowledgment of the bus control release request made by the TX19A
processor core is specified. This function is valid only if GREQ is
generated. If SREQ is generated, the TX19A processor core cannot make a
bus control release request and, therefore, this function cannot be used.
1: The bus control release request is acknowledged if the DMAC has
control of the bus. If the TX19A processor core issues a bus control
release request, the DMAC relinquishes control of the bus to the
TX19A processor core during a pause in bus operation.
0: The bus control release request is not acknowledged.
9
SIO
Source I/O
Source Type: I/O (initial value: 0)
Specifies the source device.
1: I/O device
0: Memory
Fig. 10.3.2 Channel Control Register (CCRn) (2/3)
TMP19A64(rev1.1)-10-9