TA1241ANG Datasheet, PDF (8/30 Pages) Toshiba Semiconductor – DEFLECTION PROCESSOR IC FOR TVs

I²C BUS MAP
TA1241ANG
Write data map
FUNCTION
PICTURE HEIGHT
V-LINIARITY
V-S CORRECTION
V-SHIFT. AGC, REG
v-COMPENSATION
PICTURE WIDTH
E-W PARABORA
E-W CORNER
TRAPEZIUM
H-COMP, H-CENT DAC
V-∫CORRECT, BLK-SW
V CENT DAC
ANAROG BLK-VH
ANAROG BLK-VL
CENT PAR, SAW
DYNAMIC FORCUS
IC address : 10001100 (8CH)
SUB ADDRESS
DATA
PRESET
MSB
LSB MSB
LSB MSB
LSB
RANGE
0 0 0 0 0 0 0 0 × O O O O O O O 0 1 0 0 0 0 0 0 −48~+48%
0 0 0 0 0 0 0 1 × × × O O O O O 0 0 0 1 0 0 0 0 −13~+13%
0 0 0 0 0 0 1 0 × × O O O O O O 0 0 1 0 0 0 0 0 −24~+24%
0 0 0 0 0 0 1 1 × v × A × O O × 0 0 0 0 0 0 1 0 −570~+570 mV
0 0 0 0 0 1 0 0 × × × × × OOO0 0 0 0 0 0 0 0
0~9%
0 0 0 0 0 1 0 1 × × OOOOOO0 0 1 0 0 0 0 0
1.7~6.5 V
0 0 0 0 0 1 1 0 × × OOOOOO0 0 0 0 0 0 0 0
0~4.4 V
0 0 0 0 0 1 1 1 × × × O O O O O 0 0 0 1 0 0 0 0 −3.2~+3.2%
0 0 0 0 1 0 0 0 × OOOOOOO0 1 0 0 0 0 0 0
0~2.4 V
0000
H-CENT DAC
1 001
0000
× OOO× OOO
0 0 0 0 0~9%, 1~5 V
0 0 0 0 1 0 1 0 × × B × OOOO0 0 0 0 0 0 0 0
0~4%
0 0 0 0 1 0 1 1 × OOOOOOO0 0 0 0 0 0 0 0
0.5~5 V
0 0 0 0 1 1 0 0 × × × O O O O O 0 0 0 1 0 0 0 0 −640~+640 mV
0 0 0 0 1 1 0 1 × × × O O O O O 0 0 0 1 0 0 0 0 −640~+640 mV
0 0 0 0 1 1 1 0 × OOO× OOO0 1 0 0 0 1 0 0
−4~+4 V,
−2~+2 V
0 0 0 0 1 1 1 1 × × OOOOOO0 0 0 0 0 0 0 0
−0.5~5 V
Note:
O : Used bit, × : Unused bit
A : AGC switching (DATA = 0…HIGH response, DATA = 1…LOW response)
V : Power supply switching
(DATA = 0…Stabilization power supply, DATA = 1…External power supply)
B : Blanking switch (DATA = 0…Enabled, DATA = 1…Disabled)
When the uppermost bit of the subaddress is high, auto-increment mode is set.
Read data map
FUNCTION
DATA
0
1
MSB
NON
―
―
NON
―
―
NON
―
―
IC address 10001101 (8DH)
LSB
LVP
V-GUAD E-Wout
Vout
POW
DISCRIMI-
NATION
OFF
OFF
No signal No signal
OFF
ON
ON
Signal
Signal
ON
8
2005-08-18