TLP117_14 Datasheet, PDF (6/7 Pages) Toshiba Semiconductor – PDP (Plasma Display Panel),FA (Factory Automation),High-Speed Interface

TLP117
TEST CIRCUIT 6: tpHL , tpLH
INPUT MONITORING NODE
V_IN=1.1↔5V(P.G)
(f=25MHz , duty=50%)
VCC
*CL=15pF
C_IN =22pF
SHIELD
R_IN =360Ω
GND
tr=4.5ns
0.1μF
Vo
MONITORING
NODE
V_{IN 10%}
VCC
*CL=15pF
V_O
90%
tf
CL is capacitance of the probe and JIG.
(P.G) : Pulse Generator
(example for LED drive circuit)
tpHL
tf=4.5ns
50%
VL=1.1V
GND
tr
VOH
90%
50%
10% _VOL
tpLH
CIN=22pF
CIN=47pF
INPUT MONITORING NODE ^{CIN 22 F}
f=25MHz
TC7SZ08F/FU _{RIN1=300Ω RIN2=180Ω}
VCC
P.G
RIN3=1.6kΩ
GND
5V
VCC
GND
SHIELD
0.1μF
Vo
MONITORING
NODE
VCC
*CL=15pF
CL is capacitance of the probe and JIG.
(P.G) : Pulse Generator
TEST CIRCUIT 7: Common-Mode Transient Immunity Test Circuit
SW
IF
→
A
B
1
6
VCC
5
0.1μF
V_O
3
GND ⁴
V_CC
SHIELD
V_CM
90%
V_CM 10%
tr
・SW B : IF=0mA
4V
・SW A : IF=10mA
1000V
tf
CM_H
0.4V
CM_L
CM _H
=
800(V )
t _r ^(μs)
CM _L
=
−
800(V )
t _f ^(μs)
6
2014-09-01