TLP117_14 Datasheet, PDF (5/7 Pages) Toshiba Semiconductor – PDP (Plasma Display Panel),FA (Factory Automation),High-Speed Interface

TLP117
TEST CIRCUIT 1: VOL
IF ₁
→
6
VCC
5
↑
3
GND ⁴
SHIELD
0.1μF
V_OL IOL
V↑
TEST CIRCUIT 2: VOH
1
V_CC
3
6
VCC
5
V ^VOH ↑ ^IOH
V_CC
GND ⁴
0.1μF
SHIELD
TEST CIRCUIT 3: ICCL
IF ₁
→
6
I_CCL
VCC
A
↑
5 0.1μF
V_CC
3
GND ⁴
SHIELD
TEST CIRCUIT 4: ICCH
1
6
I_CCH
VCC
A
5
0.1μF
V_CC
3
GND ⁴
SHIELD
TEST CIRCUIT 5: tpHL , tpLH
INPUT MONITORING NODE
V_IN=0↔5V(P.G)
(f=25MHz , duty=50%)
VCC
*CL=15pF
C_IN =22pF
SHIELD
R_IN=360Ω
GND
tr=4.5ns
0.1μF
Vo
MONITORING
NODE
VCC
*CL=15pF
V_{IN 10%}
V_O
90%
tf
CL is capacitance of the probe and JIG.
(P.G): Pulse Generator
tpHL
tf=4.5ns
50%
VL=0V
tr
GND
VOH
90%
50%
10% _VOL
tpLH
5
2014-09-01