TMP1962F10AXBG Datasheet, PDF (57/108 Pages) Toshiba Semiconductor – 32-Bit RISC Microprocessor

TMP1962F10AXBG
3.6.4
Read Mode and Embedded Operation Mode
The flash memory of the TMP1962F10AXBG has the following two modes of operation:
• Read mode in which array data is read
• Embedded Operation mode in which the flash array is programmed or erased
The flash memory enters Embedded Operation mode when a valid command sequence is executed in
Read mode. In Embedded Operation mode, array data can not be read.
3.6.5
Reading Array Data
The flash memory is automatically set to reading array data upon CPU reset after device power-up and
after an embedded operation is successfully completed. If an embedded operation terminated abnormally
or the flash memory is required to return to the Read mode, the Read/Reset command (software reset) or
hardware reset is used.
3.6.6
Writing Commands
The operations of the flash memory are selected by commands or command sequences written into the
internal command register. This uses the same mechanism as for JEDEC-standard EEPROMs.
Commands are made up of data sequences written at specific addresses via the command register. See
Table 3.16 on page 63 for the list of command sequences.
The command sequence being written can be canceled by issuing the Read/Reset command between
sequence cycles. The Read/Reset command clears the command register and resets the flash memory to
Read mode. Invalid command sequences also cause the flash memory to clear the command register and
return to Read mode.
3.6.7 Reset
• Read/Reset command (software reset)
The flash memory does not return to Read mode if an embedded operation terminated
abnormally. In this case, the Read/Reset command must be issued to put the flash memory back
in Read mode. The Read/Reset command may also be written between sequence cycles of the
command being written to clear the command register.
• Hardware reset ( RESET input)
As shown in Figure 3.17, the flash memory has a reset pin, which is connected to the reset signal
of the CPU. When the system drives the RESET pin to V_IL or when certain events such as a
watchdog timer time-out causes a CPU reset, the flash memory immediately terminates any
operation in progress and is reset to Read mode.
The Read/Reset command is also tied to the RESET pin to reset the flash memory to Read mode.
The embedded operation that was interrupted should be re-initiated once the flash memory is
ready to accept another command sequence because data may be corrupted.
For a description of the hardware reset operation, see Section 3.3.2, Reset Operation. When a
valid reset is achieved, the CPU reads the Reset exception vector from the flash memory and
services the Reset exception.
TMP1962F-56