TLP116_07 Datasheet, PDF (5/8 Pages) Toshiba Semiconductor – PHOTO-IC PDP(Plasma Display Panel)

TEST CIRCUIT 5 : tpHL , tpLH
I_F=12mA(P.G)
(f=5MHz , duty=50%)
VCC
INPUT
MONITORING
NODE
CL=15pF
SHIELD
R_IN=100Ω
GND
0.1uF
IF
Vo
tf
MONITORING
NODE
V_O
V_CC
CL=15pF
1.5V
CL is capacitance of the probe and JIG.
(P.G) : Pulse Generator
tpHL
TEST CIRCUIT 6 : tpHL , tpLH
V_IN=5V(P.G) ^{INPUT MONITORING NODE}
(f=5MHz , duty=50%)
CL=15pF
VCC
C_IN=27pF
SHIELD
R_IN=470Ω
GND
0.1uF
Vo
MONITORING
IF
NODE
V_CC
tf
CL=15pF
V_O
1.5V
CL is capacitance of the probe and JIG.
(P.G) : Pulse Generator
tpHL
TLP116
50%
tr
90%^VOH
10%
tpLH
VOL
50%
tr
90%^VOH
10%
tpLH
VOL
TEST CIRCUIT 7 : Common-Mode Transient Immunity Test Circuit
SW
IF
→
A
B
１
6
VCC
5 ^0.1uF
V_O
V_CC
3
GND ⁴
SHIELD
V_Cï¼­
90%
10%
tr
・SW B : IF=0mA
4V
・SW A : IF=5mA
1000Ｖ
tf
CM_H
0.4V
CM_L
CM _H
=
800(V )
t _r ^(μs)
CM
L
=
800(V )
t _f ^(μs)
5
2007-10-01