TLP116_07 Datasheet, PDF (4/8 Pages) Toshiba Semiconductor – PHOTO-IC PDP(Plasma Display Panel)

Switching Characteristics
(Unless otherwise specified, Ta=-40 to 100°C,VCC=4.5~5.5V)
Characteristic
Symbol
Test
Circuit
Conditions
Min. Typ.
Propagation delay time
to logic high output
Propagation delay time
to logic low output
Propagation delay time
to logic high output
Propagation delay time
to logic low output
Switching time dispersion
between ON and OFF
Output fall time(90-10%)
Output rise time(10-90%)
tpHL
tpLH
tpHL
tpLH
|tpHL-
tpLH|
ｔｆ
ｔｒ
IF=0→12mA
R_IN=100Ω
5
CL=15pF
IF=12→0mA
(Note 5)
—
—
—
—
V_IN=0→5V
R_IN=470Ω
6
(IF=0→8mA)
V_IN=5→0V
C_IN=27pF
CL=15pF
(IF=8→0mA) ^{(Note 5)}
IF=12mA , R_IN=100Ω,
CL=15pF (Note 5)
—
—
—
—
—
—
5
IF=0→12mA
R_IN=100Ω
—
15
CL=15pF
IF=12→0mA
(Note 5)
—
15
Common mode transient
immunity at high Level
output
Common mode transient
immunity at low level
output
CMH
CML
VCM=1000Vp-p,IF=0mA,
Vo(Min)=4V,Ta=25°C
7
VCM=1000Vp-p,IF=12mA,
Vo(Max)=0.4V,Ta=25°C
10000 —
-10000 —
*All typical values are at Ta=25°C
Note 5 : CL is approximately 15pF which includes probe and Jig/stray wiring capacitance.
TLP116
Max. Unit
60
ns
60
ns
60
ns
60
ns
30
ns
—
ns
—
ns
—
V/us
—
V/us
TEST CIRCUIT 1 : VOL
IF ₁
→
↑
3
6
VCC
0.1uF
5
V_CC
GND ⁴
V_OL IOL
V↑
SHIELD
TEST CIRCUIT 2 : VOH
1
6
VCC
5
V ^VOH ↑ ^IOH
V_CC
0.1uF
3
GND ⁴
SHIELD
TEST CIRCUIT 3 : ICCL
IF ₁
→
6
I_CCL
VCC
A
↑
5
V_CC
3
GND ⁴
SHIELD
TEST CIRCUIT 4: ICCH
1
6
I_CCH
VCC
A
5
V_CC
3
4
GND
SHIELD
4
2007-10-01