TLP112_07 Datasheet, PDF (4/7 Pages) Toshiba Semiconductor – Photo−IC Digital Logic Isolation

Test Circuit 1: Switching Time Test Circuit
I_F
PULSE INPUT
1
PW = 100μs
DUTY RATIO = 1 / 10
I_F MONITOR
3
V_CC = 5V
I_F
6
R_L
0
5
V_O
V_O
OUTPUT
4
MONITOR
TLP112
1.5V
t_pHL
5V
t_pLH
1.5V
V_OL
Test Circuit 2: Common Mode Transient Immunity Test Circuit
I_F
1
6
5
3
4
V_CM
PULSE GENERATOR
Z_O = 50Ω
V_CC = 5V
R_L
V_O
OUTPUT
MONITOR
V_CM
t_r
V_O
(I_F = 0mA)
V_O
(I_F = 16mA)
160( V )
160( V )
CΜ_H = _{tr (μs)} ,CΜ_L = _{tf (μs)}
200V
90%
10%
0V
t_f
5V
2V
0.8V
V_OL
4
2007-10-01