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TC4027BP_07 Datasheet, PDF (4/9 Pages) Toshiba Semiconductor – Dual J-K Master-Slave Flip Flop
◁
TC4027BP/BF/BFN
Dynamic Electrical Characteristics (Ta = 25°C, VSS = 0 V, CL = 50 pF)
Characteristics
Output transition time
(low to high)
Output transition time
(high to low)
Propagation delay time
(CLOCK-Q, Q )
Propagation delay time
(SET, RESET-Q, Q )
Max clock frequency
Max clock input rise time
Max clock input fall time
Min pulse width
(SET, RESET)
Min clock pulse width
Min set-up time
(J, K-CLOCK)
Min hold time
(J, K-CLOCK)
Min removal time
(SET, RESET-CLOCK)
Input capacitance
Symbol
tTLH
tTHL
tpLH
tpHL
tpLH
tpHL
fCL
trCL
tfCL
tW
tW
tSU
tH
trem
CIN
Test Condition
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
VDD (V)
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
Min Typ. Max
⎯
70 200
⎯
35 100
⎯
30
80
⎯
70 200
⎯
35 100
⎯
30
80
⎯ 150 300
⎯
75 130
⎯
60
90
⎯ 120 300
⎯
60 130
⎯
45
90
3.5
8
⎯
8.0
16
⎯
12.0 20
⎯
No limit
⎯
60 180
⎯
35
80
⎯
25
50
⎯
60 140
⎯
35
60
⎯
25
40
⎯
30 140
⎯
10
50
⎯
5
35
⎯
⎯
140
⎯
⎯
50
⎯
⎯
35
⎯
⎯
40
⎯
⎯
20
⎯
⎯
15
⎯
5
7.5
Unit
ns
ns
ns
ns
MHz
μs
ns
ns
ns
ns
ns
pF
4
2007-10-01
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