TC4027BP_07 Datasheet, PDF (2/9 Pages) Toshiba Semiconductor – Dual J-K Master-Slave Flip Flop

Truth Table
Inputs
RESET SET J
K
L
H
*
*
H
L
*
*
H
H
*
*
L
L
L
L
L
L
L
H
L
L
H
L
L
L
H
H
L
L
*
*
*: Don’t care
Δ: Level change
*^{: No change}
**^{: Change}
Logic Diagram
1/2 TC4027B
CLOCKΔ
*
*
*
Outputs
Q_{n + 1}
H
Q_{n + 1}
L
L
H
H
H
Q_n*
Q_n*
L
H
H
L
Q_{n **}
Q_n*
Q_n**
Q_{n *}
TC4027BP/BF/BFN
Absolute Maximum Ratings (Note)
Characteristics
DC supply voltage
Input voltage
Output voltage
DC input current
Power dissipation
Operating temperature range
Storage temperature range
Symbol
Rating
Unit
V_DD
V_IN
V_OUT
I_IN
P_D
T_opr
T_stg
V_SS − 0.5 to V_SS + 20
V
V_SS − 0.5 to V_DD + 0.5
V
V_SS − 0.5 to V_DD + 0.5
V
±10
mA
300 (DIP)/180 (SOIC)
mW
−40 to 85
°C
−65 to 150
°C
Note:
Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or
even destruction.
Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly
even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute
maximum ratings and the operating ranges.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
(“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test
report and estimated failure rate, etc).
2
2007-10-01