TC4027BP_07 Datasheet, PDF (1/9 Pages) Toshiba Semiconductor – Dual J-K Master-Slave Flip Flop

TC4027BP/BF/BFN
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC4027BP,TC4027BF,TC4027BFN
TC4027B Dual J-K Master-Slave Flip Flop
TC4027B is J-K master-slave flip-flop having RESET and SET
functions.
In the case of J-K made, when the clock input is given with
both RESET and SET at “L”, the output changes at rising edge of
the clock according to the states of J and K.
When SET input is placed at “H”, and RESET input is placed
at “L”, outputs become Q = “H”, and Q = “L”.
When RESET input is placed at “H”, and SET input is placed
at “L”, outputs become Q = “L”, and Q = “H”.
When both of RESET input and SET input are at “H”, outputs
become Q = “H” and Q = “H”.
Pin Assignment
Note: xxxFN (JEDEC SOP) is not available in
Japan.
TC4027BP
TC4027BF
TC4027BFN
Block Diagram
Weight
DIP16-P-300-2.54A
SOP16-P-300-1.27A
SOL16-P-150-1.27
: 1.00 g (typ.)
: 0.18 g (typ.)
: 0.13 g (typ.)
1
2007-10-01