TC59LM836DKB-30 Datasheet, PDF (38/65 Pages) Toshiba Semiconductor – MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC 288Mbits Network FCRAM2

MULTIPLE BANK WRITE TIMING (CL = 5)
TC59LM836DKB-30,-33,-40
0
1
2
3
CLK
CLK
I_RBD = 2 cycles
Command WRA LAL WRA LAL
4
5
6
7
8
9 10 11 12 13 14 15
DESL
I_RBD = 2 cycles I_RBD = 2 cycles I_RBD = 2 cycles I_RBD = 2 cycles
WRA LAL WRA LAL WRA LAL WRA LAL WRA LAL
Address UA LA UA LA
UA LA UA LA UA LA UA LA UA LA
Bank Add. ^Bank
"a"
Bank
"b"
Bank
"a"
I_RC (Bank"a") = 6 cycles
I_RC (Bank"b") = 6 cycles
Unidirectional DS/QS mode
BL = 2
DS
(input)
QS
Low
(output)
WL = 4
WL = 4
Bank
"b"
DQ
(input)
BL = 4
DS
(input)
QS
Low
(output)
Da0Da1
Db0Db1
WL = 4
WL = 4
DQ
(input)
Da0Da1Da2Da3Db0Db1Db2Db3
Bank
"c"
Bank
"d"
Bank
"a"
Da0Da1
Db0 Db1
Dc0 Dc1
Da0Da1Da2Da3Db0Db1Db2Db3Dc0 Dc1
Unidirectional DS/Free Running QS mode
BL = 2
DS
(input)
QS
(output)
WL = 4
WL = 4
DQ
(input)
Da0Da1
Db0Db1
BL = 4
DS
(input)
QS
(output)
WL = 4
WL = 4
DQ
(input)
Da0Da1Da2Da3Db0Db1Db2Db3
Note: l_RC to the same bank must be satisfied.
Da0Da1
Db0 Db1
Dc0 Dc1
Da0Da1Da2Da3Db0Db1Db2Db3Dc0 Dc1
Rev 1.3
2005-03-07 38/65