TC59LM836DKB-30 Datasheet, PDF (1/65 Pages) Toshiba Semiconductor – MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC 288Mbits Network FCRAM2

TC59LM836DKB-30,-33,-40
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
288Mbits Network FCRAM2
− 2,097,152-WORDS × 4 BANKS × 36-BITS
DESCRIPTION
Network FCRAM^TM is Double Data Rate Fast Cycle Random Access Memory. TC59LM836DKB is Network
FCRAM^TM containing 301,989,888 memory cells. TC59LM836DKB is organized as 2,097,152-words × 4 banks × 36
bits. TC59LM836DKB feature a fully synchronous operation referenced to clock edge whereby all operations are
synchronized at a clock input which enables high performance and simple user interface coexistence.
TC59LM836DKB can operate fast core cycle compared with regular DDR SDRAM.
TC59LM836DKB is suitable for Network and other applications where large memory density and low power
consumption are required. The Output Driver for Network FCRAM^TM is capable of high quality fast data transfer
under light loading condition.
FEATURES
PARAMETER
TC59LM836DKB
-30
-33
-40
CL = 4
4.0 ns
4.5 ns
5.0 ns
t_CK Clock Cycle Time (min)
CL = 5
3.5 ns
3.75 ns
4.5 ns
CL = 6
3.0 ns
3.33 ns
4.0 ns
t_RC Random Read/Write Cycle Time (min)
t_RAC Random Access Time (max)
I_DD1S Operating Current (single bank) (max)
l_DD2P Power Down Current (max)
l_DD6 Self-Refresh Current (max)
20.0 ns
20.0 ns
380 mA
100 mA
15 mA
22.5 ns
22.5 ns
360 mA
95 mA
15 mA
25 ns
25 ns
340 mA
90 mA
15 mA
• Fully Synchronous Operation
• Double Data Rate (DDR)
Data input/output are synchronized with both edges of DS / QS.
• Differential Clock (CLK and CLK ) inputs
CS , FN and all address input signals are sampled on the positive edge of CLK.
Output data (DQs and QS) is aligned to the crossings of CLK and CLK .
• Fast clock cycle time of 3.0 ns minimum
Clock: 333 MHz maximum
Data: 666 Mbps/pin maximum
• Quad Independent Banks operation
• Fast cycle and Short Latency
• Selectable Data Strobe
• Distributed Auto-Refresh cycle in 3.9 µs
• Self-Refresh
• Power Down Mode
• Variable Write Length Control
• Write Latency = CAS Latency-1
• Programable CAS Latency and Burst Length
CAS Latency = 4, 5, 6
Burst Length = 2, 4
• Organization: 2,097,152 words × 4 banks × 36 bits
• Power Supply Voltage VDD: 2.5 V ± 0.125V
VDDQ: 1.4 V ~ 1.9 V
• Low voltage CMOS I/O covered with SSTL_18 (Half strength driver) and HSTL.
• JTAG boundary scan
• Package: 144Ball BGA, 1mm × 0.8mm Ball pitch (P-TFBGA144-1119-0.80BZ)
Notice: FCRAM is trademark of Fujitsu limited, Japan.
Rev 1.3
2005-03-07 1/65