TC55V8512FT-12 Datasheet, PDF (3/10 Pages) Toshiba Semiconductor – TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS

TC55V8512J/FT-12,-15
DC CHARACTERISTICS (Ta = 0° to 70°C, V_DD = 3.3 V ± 0.3 V)
SYMBOL
PARAMETER
TEST CONDITION
MIN TYP MAX UNIT
I_IL
I_LO
I_{I (NU)}
V_OH
V_OL
I_DDO
I_DDS1
I_DDS2
Input Leakage Current
(Except NU pin)
V_IN = 0 to V_DD
−1

Output Leakage
Current
CE = V_IH or WE = V_IL or OE = V_IH,
V_OUT = 0 to V_DD
−1

Input Current
(NU pin)
V_IN = 0 to 0.8 V
V_IN = 0 to 0.2 V
−1

−1

Output High Voltage
I_OH = −2 mA
I_OH = −100 µA
2.4

V_DD − 0.2 
Output Low Voltage
I_OL = 2 mA
I_OL = 100 µA




Operating Current
CE = V_IL, I_OUT = 0 mA,
OE = V_IH,
Other Input = V_IH/V_IL
t_cycle = 12 ns


t_cycle = 15 ns


t_cycle = 20 ns


t_cycle = 25 ns


Standby Current
CE = V_IH, Other Input = V_IH or V_IL


CE = V_DD − 0.2 V, Other Input = V_DD − 0.2 V or 0.2 V


1
µA
1
µA
20
µA
1


V
0.4
0.2
170
140
mA
130
110
50
mA
4
CAPACITANCE (Ta = 25°C, f = 1 .0 MHz)
SYMBOL
PARAMETER
TEST CONDITION
C_IN
Input Capacitance
V_IN = GND
C_I/O
Input/Output Capacitance
V_I/O = GND
Note: This parameter is periodically sampled and is not 100% tested.
MAX
6
8
OPERATING MODE
MODE
CE
OE
WE
I/O1 to I/O8
Read
L
L
H
Output
Write
L
*
L
Input
Outputs Disable
L
H
H
High Impedance
Standby
H
*
*
High Impedance
* : Don’t care
Note: The NU pin must be left unconnected or tied to GND or a voltage level of less than 0.8 V.
You must not apply a voltage of more than 0.8 V to the NU.
UNIT
pF
pF
POWER
I_DDO
I_DDO
I_DDO
I_DDS
2001-12-19 3/10