TC55V8512FT-12 Datasheet, PDF (2/10 Pages) Toshiba Semiconductor – TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS

BLOCK DIAGRAM
TC55V8512J/FT-12,-15
A0
A1
V_DD
A4
A8
MEMORY CELL ARRAY
GND
A9
A12
512 × 1,024 × 8
A14
(4,194,304)
A15
A16
A17
CE
I/O1
I/O2
I/O3
I/O4
SENSE AMP
I/O5
I/O5
I/O7
I/O8
COLUMN DECODER
CE
COLUMN ADDRESS BUFFER
CLOCK
GENERATOR
A2 A3 A5 A6 A7 A10 A11A13 A18
WE
OE
CE
CE
MAXIMUM RATINGS
SYMBOL
RATING
V_DD
Power Supply Voltage
V_IN
Input Terminal Voltage
V_I/O
Input/Output Terminal Voltage
P_D
Power Dissipation
T_solder
Soldering Temperature (10s)
T_stg
Storage Temperature
T_opr
Operating Temperature
*: −1.5 V with a pulse width of 20%ŋt_RC min (4 ns max)
**: V_DD + 1.5 V with a pulse width of 20%ŋt_RC min (4 ns max)
VALUE
−0.5 to 4.6
−0.5* to 4.6
−0.5* to V_DD + 0.5**
1.4
260
−65 to 150
−10 to 85
DC RECOMMENDED OPERATING CONDITIONS (Ta = 0° to 70°C)
UNIT
V
V
V
W
°C
°C
°C
SYMBOL
PARAMETER
V_DD
Power Supply Voltage
V_IH
Input High Voltage
V_IL
Input Low Voltage
*: −1.0 V with a pulse width of 20%ŋt_RC min (4 ns max)
**: V_DD + 1.0 V with a pulse width of 20%ŋt_RC min (4 ns max)
MIN
3.0
2.0
−0.3*
TYP
MAX
UNIT
3.3
3.6
V

V_DD + 0.3**
V

0.8
V
2001-12-19 2/10