TC9496AF Datasheet, PDF (28/48 Pages) Toshiba Semiconductor – 1 Chip Audio Digital Signal Processor

TC9496AF
Command-4Dh (0100 1101): MISC
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
0
SIS SOS ERDET ZST DP7F SYRC SYRO MCKE MCKS DLSEP 0
Bit
Name
Description
Value
Operation
D15
to
¾
Fixed to 0 (zero)
¾
¾
D11
D10
SIS
Serial Input
0* Master (synchronized with the internal clock)
1 Slave (synchronized with the external clock (ELRI, EBCI))
D9
SOS
Serial output
0* Master (synchronized with the internal clock)
1 Slave (synchronized with the external clock (ELRO, EBCO))
D8
ERDET Error detection
0 Invalid
1* Valid
D7
ZST
Switches to access CROM
using Log-Linear adjustment
0 2-cycle access
1* 1-cycle access
D6
DP7F
128/256 word of DRAM (DATA
RAM) switching
0* 256 word
1 128 word
D5
SYRC Set CP at each SYNC
0 Does not reset
1* Reset
D4
SYRO Set OFP at each SYNC
0 Does not reset
1* Reset
D3
MCKE MCK pin output enable
0 Disable (fixed to L)
1* Enable (output )
D2
MCKS MCK pin output switching
0 256 fs
1* Source oscillation
D1
DLSEP
Delay RAM table area
switching
0 Does not use table
1* Use 2-k word area as the table
D0
¾
Fixed to 0 (zero)
¾
¾
Command-4Fh (0100 1111): M-RST
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
MRST 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Name
Description
Value
Operation
D15
MRST
Initialization from the micro
controller command
D14
to
¾
Fixed to 0 (zero)
D0
0* Does not initialize
1 Initializes (set to initial value.)
¾
¾
28
2002-01-11