TC9496AF Datasheet, PDF (20/48 Pages) Toshiba Semiconductor – 1 Chip Audio Digital Signal Processor

TC9496AF
3.2 Commands Description
Each command explanation is shown below. * mark in each command explanation table shows the
initial value at the time of reset.
Command-40h (0100 0000): TIMING
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SYPD SYD1 SYD0 SYPA SYA1 SYA0 SYPS SYS1 SYS0
0
CKOS CKOS CKOS CKOS CKOS CKOS
12 11 10 02 01 00
Bit
Name
Description
Value
Operation
D15
SYPD
ASP digital block sync polarity
switching
0* ASP program starts on falling edge
1 ASP program starts on rising edge
0* Signal after SYNC output
D14
SYD
ASP digital block SYNC signal ^{1 SYNC pin}
D13
[1:0]
input switching
2 ELRI pin
3 ELRO pin
D12
SYPA
DF block sync polarity
switching
0* DF-processing starts in a falling
1 DF-processing starts in a rising
0* Signal after SYNC output
D11
SYA
DF block SYNC signal input
1 SYNC pin
D10
[1:0]
switching
2 ELRI pin
3 ELRO pin
D9
SYPS
Overall system sync polarity
switching
0* Operates at polarity for SYPD, SYPA settings above.
1 Reverses all polarities for SYPD, SYPA settings above.
0* Internal SYNC signal
D8
SYS
SYNC circuit input signal
D7
[1:0]
switching selection
1 SYNC pin
2 ELRI pin
3 ELRO pin
D6
¾
Fixed to 0 (zero)
¾
¾
0* Fixed to L output
1 fs2 (internal fs ´ 2)
D5
D4
CKOS1
[2:0]
CKO1 (50 pin) pin output
selection
D3
2 fs4 (internal fs ´ 4)
3 fs8 (internal fs ´ 8)
4 fs16 (internal fs ´ 16)
5 fs32 (internal fs ´ 32)
6 fs64 (internal fs ´ 64)
7 Output XI divided by 2
0* Fixed to L output
1 fs2 (internal fs ´ 2)
D2
D1
CKOS0
[2:0]
CKO0 (49 pin) pin output
selection
D0
2 fs4 (internal fs ´ 4)
3 fs8 (internal fs ´ 8)
4 fs16 (internal fs ´ 16)
5 fs32 (internal fs ´ 32)
6 fs64 (internal fs ´ 64)
7 fs128 (internal fs ´ 128)
20
2002-01-11