TMP92CD54I Datasheet, PDF (247/343 Pages) Toshiba Semiconductor – 32-bit Micro-controller

TMP92CD54I
Mailbox receive interrupt flag register (MBRIF)
Mailbox Receive Interrupt Flag Register Low
MBRIFL
(0326H)
Read
modify-write
instructions
prohibited.
bit Symbol
Read/Write
After reset
7
MBRIF7
0
6
MBRIF6
0
5
MBRIF5
0
4
3
MBRIF4 MBRIF3
R/C
0
0
2
MBRIF2
0
Mailbox Receive Interrupt Flag Register High
1
MBRIF1
0
MBRIFH
(0327H)
Read
modify-write
instructions
prohibited.
15
14
13
12
11
10
bit Symbol MBRIF15 MBRIF14 MBRIF13 MBRIF12 MBRIF11 MBRIF10
Read/Write
R/C
After reset
0
0
0
0
0
0
9
MBRIF9
0
0
MBRIF0
0
8
MBRIF8
0
This register is provided for mailbox receive interrupts. Each bit in this register corresponds to
mailboxes 0 through 15. If mailbox “n” is directed for transmit, the corresponding interrupt flag in this
register, the <MBRIFn> flag, will always be read as “0”.
If a message in mailbox “n” has been received successfully and the mask bit <MBIMn> is set to “1”, the
corresponding receive interrupt flag <MBRIFn> will be set. If no other bit was set before in MBRIF
register, receive interrupt pulse INTCR will be generated.
If for a mailbox the mask bit in MBIM register is 0, the receive interrupt flag in MBRIF register will not
be set and no receive interrupt pulse INTCR will be generated. The information about a successful
reception could be read from the RMP register respectively.
If one or more receive interrupt flags have been set in MBRIF register and another interrupt condition
has been occurred no interrupt will be generated, but the corresponding flag in MBRIF register will be
set.
If there is one or more receive interrupt flags set after clearing one or more receive interrupt flags,
another mailbox receive interrupt pulse INTCR will be generated.
The interrupt flags in MBRIF register will be cleared by writing a “1” from the CPU to MBRIF register.
Writing a “0” has no effect.
Note that the interrupt flags in MBRIF register is checked to be 1 (active), before doing a clear-access.
92CD54I-247
2006-01-27