TC51WHM616AXBN70 Datasheet, PDF (2/11 Pages) Toshiba Semiconductor – TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS

BLOCK DIAGRAM
TC51WHM616AXBN65,70
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I/O16
CE
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
MEMORY CELL ARRAY
8,192 × 512 × 16
(67,108,864)
V_DD
GND
SENSE AMP
COLUMN ADDRESS
DECODER
REFRESH
CONTROL
REFRESH
ADDRESS
COUNTER
COLUMN ADDRESS
BUFFER
CONTROL SIGNAL ^{A0 A1 A2 A3 A4 A5 A6 A7 A8}
GENERATOR
CE
WE
OE
UB
LB
CE1
CE
CE2
OPERATION MODE
MODE
CE1 CE2 OE WE LB UB Add I/O1 to I/O8 I/O9 to I/O16
Read(Word)
L
H
L
H
L
L
X
Read(Lower Byte)
L
H
L
H
L
H
X
Read(Upper Byte)
L
H
L
H
H
L
X
Write(Word)
L
H
X
L
L
L
X
Write(Lower Byte)
L
H
X
L
L
H
X
Write(Upper Byte)
L
H
X
L
H
L
X
Outputs Disabled
L
H
H
H
X
X
X
Standby
H
H
X
X
X
X
X
Deep Power-down Standby H
L
X
X
X
X
X
D_OUT
D_OUT
High-Z
D_IN
D_IN
Invalid
High-Z
High-Z
High-Z
D_OUT
High-Z
D_OUT
D_IN
Invalid
D_IN
High-Z
High-Z
High-Z
Notes: L = Low-level Input(V_IL), H = High-level Input(V_IH), X = V_IH or V_IL, High-Z = High-impedance
POWER
I_DDO
I_DDO
I_DDO
I_DDO
I_DDO
I_DDO
I_DDO
I_DDS
I_DDSD
2002-08-22 2/11