TMP1941AF Datasheet, PDF (182/354 Pages) Toshiba Semiconductor – 32-Bit TX System RISC

TMP1941AF
TMRB1 Mode Register
7
6
TB1MOD
Name
(0xFFFF_F192) _Read/Write


R/W
Reset Value
0
0
Must be written as 00.
Function
5
4
3
2
TB1CP0 TB1CPM1 TB1CPM0 TB1CLE
W*
R/W
1
0
0
0
Software Capture triggers
UC1 clear
capture _{00: Disabled}
control
0: Capture _{01: TB1IN0↑TB1IN1↑} 0: Disable
1: Don’t
care
10: TB1IN0↑TB1IN0↓ ^{1: Enable}
11: TA1OUT↑TA1OUT↓
1
0
TB1CLK1 TB1CLK0
0
0
TMRB1 clock source
00: TB1IN0 input
01: φT1
10: φT4
11: φT16
Up-counter (UC1) clear control
0 Disabled
1 UC1 is reset upon a match with TB1RG1.
Capture triggers
00 Capture disabled
Latches UC1 value into TB1CP0 at rising edges of TB1IN0
01
Latches UC1 value into TB1CP1 at rising edges of TB1IN1.
Latches UC1 value into TB1CP0 at rising edges of TB1IN0.
10
Latches UC1 value into TB1CP1 at falling edges of TB1IN0.
Latches UC1 value into TB1CP0 at rising edges of TA1OUT.
11
Latches UC1 value into TB1CP1 at falling edges of TA1OUT.
Software capture
0 Latches UC1 value into TB1CP0.
1 Don’t care
Figure 12.8 TMRB1 Mode Register
TMP1941AF-142
2003-03-27