TMP88FW45FG Datasheet, PDF (157/276 Pages) Toshiba Semiconductor – 8 Bit Microcontroller

TMP88FW45FG
CMPU
CMPV
CMPW
Set PWM pulse width
This comparison register determines the pulse widths output in the respective UVW
phases. This register is dual-buffered, and the pulse widths are determined by comparing
the buffer and PWM counter.
Waveform Synthesis Circuit Registers [Addresses (PMD1 and PMD2)]
MDCRB
7
6
5
4
3
2
1
0
(01FAFH)
–
–
–
–
–
–
PWMCK
(01FDFH)
(Initial value: **** **00)
00: fc/2 [Hz] (100 ns at 20 MHz)
01: fc/2² (200 ns at 20 MHz)
1, 0 PWMCK
PWM counterSelect clock
10: fc/2³ (400 ns at 20 MHz)
R/W
11: fc/2⁴ (800 ns at 20 MHz)
Note: When changing setting, keep the PWMEN bit reset to “0” (disable wave form synthesis function).
MDCRA
(01FAEH)
(01FDEH)
7
HLFINT
6
DTYMD
5
POLH
4
POLL
3
2
PINT
1
0
PWMMD PWMEN (Initial value: 0000 0000)
7
HLFINT
Select half-period interrupt
0: Interrupt as specified in PINT
1: Interrupt every half period when PINT = 00
6
DTYMD
DUTY mode
0: U phase in common
1: Three phases independent
5
POLH
Upper-phase port polarity
0: Active low
1: Active high
0: Active low
4
POLL
Lower-phase port polarity
1: Active high
R/W
00: Interrupt every period
3, 2 PINT
01: Interrupt once every 2 periods
Select PWM interrupt (trigger)
10: Interrupt once every 4 periods
11: Interrupt once every 8 periods
1
PWMMD
PWM mode
0: PWM mode0 (Edge: Sawtooth wave)
1: PWM mode1 (Center: Triangular wave)
0
PWMEN
Enable/disable waveform syn- 0: Disable
thesis function
1: Enable (Waveform output)
DTR
7
(01FBEH)
–
(01FEEH)
6
5
4
3
2
1
0
–
D5
D4
D3
D2
D1
D0 (Initial value: **00 0000)
5 to 0 DTR
Dead time
2³/fc × 6 bit (maximum 25.2 µs at 20 MHz)
R/W
Note: When changing setting, keep the MDCRA<PWMEN> bit reset to "0" (disable wave form synthesis function).
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