THNCF064MMA Datasheet, PDF (15/47 Pages) Toshiba Semiconductor – The THNCFxxxxMA series CompactFlash card is a flash technology based with ATA interface flash memory card

Preliminary
THNCFxxxxMA Series
2. Configuration and Status register (Address 202h)
This register is used for observing the state of the card.
bit7
bit6
bit5
bit4
CHGED
SIGCHG
IOIS8
0
Note: initial value Ë  00H
bit3
bit2
bit1
bit0
0
PWD
INTR
0
Name
CHGED
(CARD->)
SIGCHG
(HOST->)
IOIS8
(HOST->)
PWD
(HOST->)
INTR
(CARD->)
R/W
Function
This bit indicates that CRDY/−BSY bit on Pin Replacement register is set to “1”. When CHGED bit
R
is set to “1”, −STSCHG pin is held “L” at the condition of SIGCHG bit set to “1” and the card
configured for the I/O interface.
This bit is set or reset by the host for enabling and disabling the status-change signal (−STSCHG
R/W
pin). When the card is configured I/O card interface and this bit is set “1”, −STSCHG pin is
controlled by CHGED bit. If this bit is set to “0”, −STSCHG pin is kept “H”.
The host sets this field to “1” when it can provide I/O cycles only with on 8 bit data bus (D7 to D0).
R/W
When this bit is set to “1”, the card enters sleep state (Power Down mode). When this bit is reset
to “0”, the card transfers to idle state (active mode). RRDY/BSY bit on Pin Replacement Register
R/W
becomes BUSY when this bit is changed. RRDY/BSY will not become Ready until the power state
requested has been entered. This card automatically powers down when it is idle and powers
back up when it receives a command.
This bit indicates the internal state of the interrupt request. This bit state is available whether I/O
card interface has been configured or not. This signal remains true until the condition, which
R
caused the interrupt request, has been serviced. If the −IEN bit in the Device Control Register
disables interrupts, this bit is a zero.
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