TA1296FN Datasheet, PDF (13/22 Pages) Toshiba Semiconductor – Down-Converter IC with PLL for Satellite Tuner

TA1296FN
[[BYTE 5]]
Byte 5 can be used to select Test Mode and to control the output ports (band 1 and band 2).
Bit 1, bit 2 and bit 3 (T2, T1 and T0) can be used to set up Test Mode. These bits determine the
phase comparator reference signal output and the counter divider output.
Bit 5 (for B2) and bit 8 (for B1) can be used to control the output ports. When either of these
bits is set to 0, the corresponding port is turned OFF. When either of these bits is set to 1, the
corresponding port is turned ON. Each output port can be driven at less than 10 mA.
B) Read mode (status request)
When Read Mode is selected, the power-on reset operation status, phase comparator lock detector
output status, comparator input port status and 5-level AD converter pin input voltage status are
output to the master device.
Bit 1 (POR) indicates the power-on reset operation status. When the power supply voltage VCC2 is
cut off, this bit is set to 1. Bit 1 is reset to 0 when a voltage of 3 V or higher is applied to VCC2 and
transmission is requested in Read Mode. At this point the new status is output. (bit 1 is also set to 1
when VCC2 is turned ON.)
Bit 2 (FL) indicates the phase comparator lock status. When the phase comparator is locked, 1 is
output. When the phase comparator is unlocked, 0 is output.
Bit 3, bit 4 and bit 5 (I-P3, I-P2, I-P1) indicate the input comparator status. I-P3, I-P2 and I-P1
indicate the status of input ports I-P3, I-P2 and I-P1 (pins 13, 14 and 15) respectively. The input
voltage status for each comparator input port pin is output to the master device. High is indicated by
1. Low is indicated by 0. High represents a voltage of above 2.7 V applied to the corresponding pin.
Low represents an applied voltage of below 1.5 V.
Bit 6, bit 7 and bit 8 (A2, A1 and A0) indicate the status of the five-level AD converter. The voltage
applied to the AD converter input pin (pin 3) is output after being resolved to one of five levels.
To see the bit values output for the five resolution levels and to see how these levels correspond to
the voltage applied to the AD converter input pin (ADCin-pin 12), please refer to the table entitled A2,
A1 and A0: Five-level AD converter status (e.g. the AFT output voltage data can be given to the
master device).
Data Format
A) Write mode
MSB
LSB
1 Address Byte
2 Divider Byte 1
3 Divider Byte 2
4 Control Byte
5 Band SW Byte
1
1
0
0
0
MA1
MA0 R/W = 0 ACK
0
N14
N13
N12
N11
N10
N9
N8
ACK
N7
N6
N5
N4
N3
N2
N1
N0 ACK (L)
1
´
N15
CP1
CP0
´
Rs
OS ACK (L)
T2
T1
T0
´
B2
´
´
B1 ACK (L)
´: Don’t care
ACK: Acknowledged
(L): Latch and transfer timing
B) Read mode
MSB
LSB
1 Address Byte
2 Status Byte
1
1
POR
FL
0
0
0
MA1
MA0 R/W = 1 ACK
I-P3
I-P2
I-P1
A2
A1
A0
¾
ACK: Acknowledged
13
2002-02-12