TA1296FN Datasheet, PDF (10/22 Pages) Toshiba Semiconductor – Down-Converter IC with PLL for Satellite Tuner

Bus Line Characteristics
Parameter
SCL clock frequency
Bus free time between a STOP and
START conditions
Hold time for repeated START
condition
SCL clock low period
SCL clock high period
Set-up time for repeated START
condition
Data hold time
Data set-up time
Rise time for SDA and SCL signals
Fall time for SDA and SCL signals
Set-up time for STOP condition
Symbol
fSCL
t_BUF
Test
Circuit
Test Condition
t_HD; STA
t_LOW
t_HIGH
f_SU; STA
t_HD; DAT
t_SU; DAT
tR
tF
tsU; STO
¾
Please refer to data timing
chart.
TA1296FN
Min Typ. Max Unit
0
¾
100 kHz
4.7
¾
¾
ms
4
¾
¾
ms
4.7
¾
¾
ms
4
¾
¾
ms
4.7
¾
¾
ms
0
¾
¾
ms
250 ¾
¾
ns
¾
¾ 1000 ns
¾
¾ 300 ns
4
¾
¾
ms
SDA
t_BUF
SCL
t_LOW tR
tF
t_HD; STA
t_HD; STA _{tHD; DAT}
t_HIGH t_SU; DAT t_SU; STA
P
S
Sr
tSU; STO
P
Figure 1 I²C Bus Data Timing Chart (rising-edge timing)
10
2002-02-12