TCD2560D Datasheet, PDF (10/15 Pages) Toshiba Semiconductor – TOSHIBA CCD Image Sensor CCD (charge coupled device)

TCD2560D
Timing Requirements
Characteristics
Pulse timing of SH and f1
SH pulse rise time, fall time
SH pulse width
Pulse timing of SH and CP
Pulse timing of SH and CP (line clamp mode)
f1, f2 pulse rise time, fall time
RS pulse rise time, fall time
RS pulse width
Pulse timing of RS and CP
Pulse timing of f1A, f2A and CP
CP pulse rise time, fall time
CP pulse width
(Note 13)
Reference level settle time (bit clamp mode)
Video data delay time
(Note 14)
Reference level settle time (line clamp mode)
Note 12: Typ. is the case of f_RS = 1.0 MHz
Note 13: Line clamp Mode inside ( ).
Note 14: Load resistance is 100 kW
Note 15: Typical settle time to about 1% of final value
Note 16: Typical settle time to about 1% of the peak
Symbol
t1
t5
t2, t4
t3
t6
t7
t8, t9
t10, t11
t12
t13
t14
t15, t16
t17
t18
t19
t20
Min ^Typ. Max Unit
(Note 12)
120 1000 ¾
ns
800 1000 ¾
0
50
¾
ns
3000 5000 ¾
ns
200 500
¾
ns
10
100
¾
ns
0
50
¾
ns
0
20
¾
ns
30
80
¾
ns
10
20
¾
ns
0
20
¾
ns
0
20
¾
ns
40
80
(3000) (5000)
¾
ns
45
¾
35
ns
(Note 16)
60
¾
40
ns
(Note 15)
70
¾
60
ns
(Note 16)
Clamp Mode
Clamp Means
Bit Clamp
Line Clamp
CP Input Pulse
CP Pulse
CP = SH or CP = DC 5 V
10
2002-12-25