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TC55V4000ST-70 Datasheet, PDF (1/10 Pages) Toshiba Semiconductor – 524,288-WORD BY 8-BIT STATIC RAM
TC55V4000ST-70,-85
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
524,288-WORD BY 8-BIT STATIC RAM
DESCRIPTION
The TC55V4000ST is a 4,194,304-bit static random access memory (SRAM) organized as 524,288 words by 8 bits.
Fabricated using Toshiba's CMOS Silicon gate process technology, this device operates from a single 2.3 to 3.6 V
power supply. Advanced circuit technology provides both high speed and low power at an operating current of 3
mA/MHz and a minimum cycle time of 70 ns. It is automatically placed in low-power mode at 0.5 µA standby
current (at VDD = 3 V, Ta = 25°C) when chip enable ( CE ) is asserted high. There are two control inputs. CE is
used to select the device and for data retention control, and output enable ( OE ) provides fast memory access. This
device is well suited to various microprocessor system applications where high speed, low power and battery
backup are required. The TC55V4000ST is available in a normal pinout plastic 32-pin thin-small-outline package
(TSOP).
FEATURES
• Low-power dissipation
Operating: 10.8 mW/MHz (typical)
• Single power supply voltage of 2.3 to 3.6 V
• Power down features using CE
• Data retention supply voltage of 1.5 to 3.6 V
• Direct TTL compatibility for all inputs and outputs
• Standby Current (maximum):
3.6 V
3.0 V
7 µA
5 µA
• Access Times (maximum):
TC55V4000ST
-70
-85
Access Time
70 ns
85 ns
CE Access Time
70 ns
85 ns
OE Access Time
35 ns
45 ns
• Package:
TSOPᶗ32-P-0.50 (ST)
(Weight: 0.24 g typ)
PIN ASSIGNMENT (TOP VIEW)
32 PIN TSOP
16
1
17
32
(Normal pinout)
PIN NAMES
A0~A18
R/W
OE
CE
I/O1~I/O8
VDD
GND
Address Inputs
Read/Write Control
Output Enable
Chip Enable
Data Inputs/Outputs
Power
Ground
Pin No.
Pin Name
Pin No.
Pin Name
12
A11 A9
17 18
A3 A2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
A8 A13 R/W A17 A15 VDD A18 A16 A14 A12 A7 A6 A5 A4
19 20 21 22 23 24 25 26 27 28 29 30 31 42
A1 A0 I/O1 I/O2 I/O3 GND I/O4 I/O5 I/O6 I/O7 I/O8 CE A10 OE
2001-11-30 1/10