TMS320C6748_16 Datasheet, PDF (99/273 Pages) Texas Instruments – Fixed- and Floating-Point DSP

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TMS320C6748
SPRS590F – JUNE 2009 – REVISED MARCH 2014
Table 6-10. PSC1 Default Module Configuration
LPSC
Number
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Module Name
EDMA3 Channel Controller 1
USB0 (USB2.0)
USB1 (USB1.1)
GPIO
UHPI
EMAC
DDR2 (and SCR_F3)
McASP0 ( + McASP0 FIFO)
SATA
VPIF
SPI 1
I2C 1
UART 1
UART 2
McBSP0 ( + McBSP0 FIFO)
McBSP1 ( + McBSP1 FIFO)
LCDC
eHRPWM0/1
MMCSD1
uPP
ECAP0/1/2
EDMA3 Transfer Controller 2
—
—
SCR_F0 (and bridge F0)
SCR_F1 (and bridge F1)
SCR_F2 (and bridge F2)
SCR_F6 (and bridge F3)
SCR_F7 (and bridge F4)
SCR_F8 (and bridge F5)
Bridge F7 (DDR Controller path)
On-chip RAM (including SCR_F4
and bridge F6)
Power Domain
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
—
—
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
PD_SHRAM
Default Module State
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
—
—
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Auto Sleep/Wake Only
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Yes
Yes
Yes
Yes
Yes
Yes
Yes
—
Copyright © 2009–2014, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
99
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