TMS320C6748_16 Datasheet, PDF (165/273 Pages) Texas Instruments – Fixed- and Floating-Point DSP

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TMS320C6748
SPRS590F – JUNE 2009 – REVISED MARCH 2014
Table 6-69. General Timing Requirements for SPI0 Slave Modes⁽¹⁾
NO.
9 t_c(SPC)S
10 t_w(SPCH)S
11 t_w(SPCL)S
Cycle Time, SPI0_CLK, All Slave Modes
Pulse Width High, SPI0_CLK, All Slave Modes
Pulse Width Low, SPI0_CLK, All Slave Modes
Polarity = 0, Phase = 0,
to SPI0_CLK rising
Setup time, transmit data
12
t_{su(SOMI_SPC)S}
written to SPI before initial
clock edge from
master.^{(3) (4)}
Polarity = 0, Phase = 1,
to SPI0_CLK rising
Polarity = 1, Phase = 0,
to SPI0_CLK falling
Polarity = 1, Phase = 1,
to SPI0_CLK falling
Polarity = 0, Phase = 0,
from SPI0_CLK rising
13 t_{d(SPC_SOMI)S}
Polarity = 0, Phase = 1,
Delay, subsequent bits valid _{from SPI0_CLK falling}
on SPI0_SOMI after
transmit edge of SPI0_CLK ^{Polarity = 1, Phase = 0,}
from SPI0_CLK falling
Polarity = 1, Phase = 1,
from SPI0_CLK rising
Polarity = 0, Phase = 0,
from SPI0_CLK falling
Output hold time,
14 t_{oh(SPC_SOMI)S} SPI0_SOMI valid after
receive edge of SPI0_CLK
Polarity = 0, Phase = 1,
from SPI0_CLK rising
Polarity = 1, Phase = 0,
from SPI0_CLK rising
Polarity = 1, Phase = 1,
from SPI0_CLK falling
Polarity = 0, Phase = 0,
to SPI0_CLK falling
Input Setup Time,
15 t_{su(SIMO_SPC)S} SPI0_SIMO valid before
receive edge of SPI0_CLK
Polarity = 0, Phase = 1,
to SPI0_CLK rising
Polarity = 1, Phase = 0,
to SPI0_CLK rising
Polarity = 1, Phase = 1,
to SPI0_CLK falling
Polarity = 0, Phase = 0,
from SPI0_CLK falling
Input Hold Time,
16 t_{ih(SPC_SIMO)S} SPI0_SIMO valid after
receive edge of SPI0_CLK
Polarity = 0, Phase = 1,
from SPI0_CLK rising
Polarity = 1, Phase = 0,
from SPI0_CLK rising
Polarity = 1, Phase = 1,
from SPI0_CLK falling
1.3V, 1.2V
MIN
40 ⁽²⁾
MAX
18
18
2P
1.1V
MIN
50 ⁽²⁾
MAX
22
22
2P
1.0V
MIN
60 ⁽²⁾
MAX
UNIT
ns
27
ns
27
ns
2P
2P
2P
2P
ns
2P
2P
2P
2P
2P
2P
17
20
27
17
20
27
ns
17
20
27
17
20
27
0.5S-6
0.5S-16
0.5S-20
0.5S-6
0.5S-16
0.5S-20
ns
0.5S-6
0.5S-16
0.5S-20
0.5S-6
0.5S-16
0.5S-20
1.5
1.5
1.5
1.5
1.5
1.5
ns
1.5
1.5
1.5
1.5
1.5
1.5
4
4
5
4
4
5
ns
4
4
5
4
4
5
(1) P = SYSCLK2 period; S = t_c(SPC)S (SPI slave bit clock period)
(2) This timing is limited by the timing shown or 3P, whichever is greater.
(3) First bit may be MSB or LSB depending upon SPI configuration. SO(0) refers to first bit and SO(n) refers to last bit output on
SPI0_SOMI. SI(0) refers to the first bit input and SI(n) refers to the last bit input on SPI0_SIMO.
(4) Measured from the termination of the write of new data to the SPI module, In analyzing throughput requirements, additional internal bus
cycles must be accounted for to allow data to be written to the SPI module by the CPU.
Copyright © 2009–2014, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications 165
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