TM4C1231C3PM Datasheet, PDF (987/1145 Pages) Texas Instruments – Tiva™ TM4C1231C3PM Microcontroller

Tiva^™ TM4C1231C3PM Microcontroller
Register 4: I²C Master Timer Period (I2CMTPR), offset 0x00C
This register is programmed to set the timer period for the SCL clock and assign the SCL clock to
either standard or high-speed mode.
I2C Master Timer Period (I2CMTPR)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
Offset 0x00C
Type RW, reset 0x0000.0001
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
HS
TPR
Type RO
RO
RO
RO
RO
RO
RO
RO
WO
RW
RW
RW
RW
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Bit/Field
31:8
7
Name
reserved
HS
Type
RO
WO
Reset Description
0x0000.00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0
High-Speed Enable
Value Description
0 The SCL Clock Period set by TPR applies to Standard mode
(100 Kbps), Fast-mode (400 Kbps), or Fast-mode plus (1 Mbps).
1 The SCL Clock Period set by TPR applies to High-speed mode
(3.33 Mbps).
6:0
TPR
RW
0x1
Timer Period
This field is used in the equation to configure SCL_PERIOD:
SCL_PERIOD = 2×(1 + TPR)×(SCL_LP + SCL_HP)×CLK_PRD
where:
SCL_PRD is the SCL line period (I²C clock).
TPR is the Timer Period register value (range of 1 to 127).
SCL_LP is the SCL Low period (fixed at 6).
SCL_HP is the SCL High period (fixed at 4).
CLK_PRD is the system clock period in ns.
June 12, 2014
987
Texas Instruments-Production Data