TM4C1231C3PM Datasheet, PDF (137/1145 Pages) Texas Instruments – Tiva™ TM4C1231C3PM Microcontroller

Tiva^™ TM4C1231C3PM Microcontroller
Register 18: Interrupt 128-138 Set Pending (PEND4), offset 0x210
Note: This register can only be accessed from privileged mode.
The PEND4 register forces interrupts into the pending state and shows which interrupts are pending.
Bit 0 corresponds to Interrupt 128; bit 10 corresponds to Interrupt 138. See Table 2-9 on page 94
for interrupt assignments.
Interrupt 128-138 Set Pending (PEND4)
Base 0xE000.E000
Offset 0x210
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
INT
Type RO
RO
RO
RO
RO
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:11
10:0
Name
reserved
INT
Type
Reset Description
RO 0x0000.000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
RW
0x0
Interrupt Set Pending
Value
0
1
Description
On a read, indicates that the interrupt is not pending.
On a write, no effect.
On a read, indicates that the interrupt is pending.
On a write, the corresponding interrupt is set to pending
even if it is disabled.
If the corresponding interrupt is already pending, setting a bit has no
effect.
A bit can only be cleared by setting the corresponding INT[n] bit in
the UNPEND4 register.
June 12, 2014
137
Texas Instruments-Production Data