TM4C1231C3PM Datasheet, PDF (922/1145 Pages) Texas Instruments – Tiva™ TM4C1231C3PM Microcontroller

Synchronous Serial Interface (SSI)
For continuous back-to-back transfers, the SSInFss pin is held Low between successive data
words, and termination is the same as that of the single word transfer.
15.3.4.5
Freescale SPI Frame Format with SPO=1 and SPH=0
Single and continuous transmission signal sequences for Freescale SPI format with SPO=1 and
SPH=0 are shown in Figure 15-7 on page 922 and Figure 15-8 on page 922.
Figure 15-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0
SSInClk
SSInFss
SSInRx
SSInTx
MSB
MSB
4 to 16 bits
LSB
Q
LSB
Note: Q is undefined.
Figure 15-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0
SSInClk
SSInFss
SSInTx/SSInRx _LSB
MSB
LSB
4 to 16 bits
MSB
In this configuration, during idle periods:
■ SSInClk is forced High
■ SSInFss is forced High
■ The transmit data line SSInTx is tristated
■ When the SSI is configured as a master, it enables the SSInClk pad
■ When the SSI is configured as a slave, it disables the SSInClk pad
If the SSI is enabled and valid data is in the transmit FIFO, the start of transmission is signified by
the SSInFss master signal being driven Low, causing slave data to be immediately transferred
onto the SSInRx line of the master. The master SSInTx output pad is enabled.
One-half period later, valid master data is transferred to the SSInTx line. Once both the master and
slave data have been set, the SSInClk master clock pin becomes Low after one additional half
922
June 12, 2014
Texas Instruments-Production Data