TMS320C6457CCMH Datasheet, PDF (97/217 Pages) Texas Instruments – Communications Infrastructure Digital Signal Processor

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Table 7-3
TMS320C6457
Communications Infrastructure Digital Signal Processor
SPRS582B—July 2010
C6457 EDMA3 Channel Synchronization Events ⁽¹⁾ (Part 2 of 2)
EDMA Channel
28
29
30
31
32
33
34
35 - 39
40
41 - 43
44
45
46 - 47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
End of Table 7-3
Event Name
VCP2REVT
VCP2XEVT
TCP2AREVT
TCP2AXEVT
UREVT
TCP2BREVT
TCP2BXEVT
-
UXEVT
-
ICREVT
ICXEVT
-
GPINT0
GPINT1
GPINT2
GPINT3
GPINT4
GPINT5
GPINT6
GPINT7
GPINT8
GPINT9
GPINT10
GPINT11
GPINT12
GPINT13
GPINT14
GPINT15
VCP2 Receive Event
VCP2 Transmit Event
TCP2_A Receive Event
TCP2_A Transmit Event
UTOPIA Receive Event
TCP2_B Receive Event
TCP2_B Transmit Event
None
UTOPIA Transmit Event
None
I²C Receive Event
I²C Transmit Event
None
GPIO event 0
GPIO event 1
GPIO event 2
GPIO event 3
GPIO event 4
GPIO event 5
GPIO event 6
GPIO event 7
GPIO event 8
GPIO event 9
GPIO event 10
GPIO event 11
GPIO event 12
GPIO event 13
GPIO event 14
GPIO event 15
Event Description
1 In addition to the events shown in this table, each of the 64 channels can also be synchronized with the transfer completion or alternate transfer completion events. For more
detailed information on EDMA event-transfer chaining, see the TMS320C6457 DSP Enhanced DMA (EDMA3) Controller User's Guide (literature number SPRUGK6).
2 HPI boot is terminated using a DSP interrupt. The DSP interrupt is registered in bit 0 (channel 0) of the EDMA Event Register (ER). This event must be cleared by software before
triggering transfers on DMA channel 0.
7.4.3 EDMA3 Peripheral Register Description(s)
Table 7-4
EDMA3 Registers (Part 1 of 15)
Hex Address
02A0 0000
02A0 0004
02A0 0008 - 02A0 00FC
02A0 0100
02A0 0104
02A0 0108
Acronym
PID
CCCFG
-
DCHMAP0
DCHMAP1
DCHMAP2
Register Name
Peripheral ID Register
EDMA3CC Configuration Register
Reserved
DMA Channel 0 Mapping Register
DMA Channel 1 Mapping Register
DMA Channel 2 Mapping Register
2009 Texas Instruments Incorporated
C64x+ Peripheral Information and Electrical Specifications 97