TMS320C6457CCMH Datasheet, PDF (188/217 Pages) Texas Instruments – Communications Infrastructure Digital Signal Processor

TMS320C6457
Communications Infrastructure Digital Signal Processor
SPRS582B—July 2010
Table 7-102 TCP2_B Registers (Part 2 of 2)
EDMA Bus Hex Address Range
5010 000C
5010 0010
5010 0014
5010 0018
5010 001C
5010 0020
5010 0024
5010 0028
5010 002C
5010 0030
5010 0034
5010 0038
5010 003C
5010 0040
5010 0044
5010 0048
5011 0000
5013 0000
5014 0000
5015 0000
5016 0000
5017 0000
5018 0000
5019 0000
501A 0000
501B 0000
N/A
N/A
N/A
N/A
N/A
N/A
End of Table 7-102
Configuration Bus Hex Address Range
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
02BA 0100
02BA 014C
02BA 0150
02BA 0160
02BA 0168
02BA 0170
02BA 0174 - 02BB FFFF
Acronym
TCPIC3
TCPIC4
TCPIC5
TCPIC6
TCPIC7
TCPIC8
TCPIC9
TCPIC10
TCPIC11
TCPIC12
TCPIC13
TCPIC14
TCPIC15
TCPOUT0
TCPOUT1
TCPOUT2
X0
W0
W1
I0
O0
S0
T0
C0
B0
A0
TCPPID
TCPEXE
TCPEND
TCPERR
TCPSTAT
TCPEMU
-
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Register Name
TCP2 Input Configuration Register 3
TCP2 Input Configuration Register 4
TCP2 Input Configuration Register 5
TCP2 Input Configuration Register 6
TCP2 Input Configuration Register 7
TCP2 Input Configuration Register 8
TCP2 Input Configuration Register 9
TCP2 Input Configuration Register 10
TCP2 Input Configuration Register 11
TCP2 Input Configuration Register 12
TCP2 Input Configuration Register 13
TCP2 Input Configuration Register 14
TCP2 Input Configuration Register 15
TCP2 Output Parameters Register 0
TCP2 Output Parameters Register 1
TCP2 Output Parameters Register 2
TCP2 Data/Sys and Parity Memory
TCP2 Extrinsic Mem 0
TCP2 Extrinsic Mem 1
TCP2 Interleaver Memory
TCP2 Output/Decision Memory
TCP2 Scratch Pad Memory
TCP2 Beta State Memory
TCP2 CRC Memory
TCP2 Beta Prolog Memory
TCP2 Alpha Prolog Memory
TCP2 Peripheral Identification Register
TCP2 Execute Register
TCP2 Endianness Register
TCP2 Error Register
TCP2 Status Register
TCP2 Emulation Register
Reserved
188 C64x+ Peripheral Information and Electrical Specifications
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