TMS320C6457CCMH Datasheet, PDF (37/217 Pages) Texas Instruments – Communications Infrastructure Digital Signal Processor

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Table 2-6
Signal Name
ABA1
ABA0
ACE5
ACE4
ACE3
ACE2
ABE07
ABE06
ABE05
ABE04
ABE03
ABE02
ABE01
ABE00
AHOLDA
AHOLD
ABUSREQ
AECLKIN
AECLKOUT
AAWE/ASWE
AARDY
AR/W
AAOE/ASOE
ASADS/ASRE
TMS320C6457
Communications Infrastructure Digital Signal Processor
SPRS582B—July 2010
Terminal Functions (Part 5 of 22)
Ball No.
V24
V25
V26
U27
W25
W26
W28
L25
L28
L27
Y28
W27
Y24
Y25
N25
R28
L26
N28
V28
AA24
K28
W24
AE25
R25
Type IPD/IPU Description
EMIFA (64-BIT) — CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY
O/Z
IPD EMIFA bank address control (ABA[1:0]). Active-low bank selects for the 64-bit EMIFA.
• When interfacing to 16-bit Asynchronous devices, ABA1 carries bit 1 of the byte address.
O/Z
IPD _{• For an 8-bit Asynchronous interface, ABA[1:0] are used to carry bits 1 and 0 of the byte address.}
EMIFA memory space enables.
• Enabled by bits 28 through 31 of the word address
O/Z
IPU • Only one pin is asserted during any external data access
NOTE: The C6457 device does not have ACE0 and ACE1 pins.
EMIFA byte-enable control.
O/Z
IPU
• Decoded from the low-order address bits. The number of address bits or byte enables used
depends on the width of external memory.
• Byte-write enables for most types of memory.
EMIFA (64-BIT) — BUS ARBITRATION
O
IPU EMIFA hold-request-acknowledge to the host
I
IPU EMIFA hold request from the host
O
IPU EMIFA bus request output
EMIFA (64-BIT) — ASYNCHRONOUS/SYNCHRONOUS MEMORY CONTROL
EMIFA external input clock. The EMIFA input clock (AECLKIN or SYSCLK7 clock) is selected at
I
IPD ^{reset via the pullup/pulldown resistor on the GPIO[15] pin.}
NOTE: AECLKIN is the default for the EMIFA input clock.
O/Z
IPD EMIFA output clock [at EMIFA input clock (AECLKIN or SYSCLK7) frequency]
O/Z
IPU Asynchronous memory write-enable/Programmable synchronous interface write-enable
I
IPU Asynchronous memory ready input
O/Z
IPU Asynchronous memory read/write
O/Z
IPU Asynchronous/Programmable synchronous memory output-enable
Programmable synchronous address strobe or read-enable
• For programmable synchronous interface, the R_ENABLE field in the Chip Select x
O/Z
IPU
Configuration Register selects between ASADS and ASRE:
– If R_ENABLE = 0, then the ASADS/ASRE signal functions as the ASADS signal.
– If R_ENABLE = 1, then the ASADS/ASRE signal functions as the ASRE signal.
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Device Overview 37