TM4C1233H6PZ Datasheet, PDF (949/1243 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C1233H6PZ Microcontroller
Figure 15-3. TI Synchronous Serial Frame Format (Continuous Transfer)
SSInClk
SSInFss
SSInTx/SSInRx
MSB
LSB
4 to 16 bits
15.3.4.2
Freescale SPI Frame Format
The Freescale SPI interface is a four-wire interface where the SSInFss signal behaves as a slave
select. The main feature of the Freescale SPI format is that the inactive state and phase of the
SSInClk signal are programmable through the SPO and SPH bits in the SSICR0 control register.
SPO Clock Polarity Bit
When the SPO clock polarity control bit is clear, it produces a steady state Low value on the SSInClk
pin. If the SPO bit is set, a steady state High value is placed on the SSInClk pin when data is not
being transferred.
SPH Phase Control Bit
The SPH phase control bit selects the clock edge that captures data and allows it to change state.
The state of this bit has the most impact on the first bit transmitted by either allowing or not allowing
a clock transition before the first data capture edge. When the SPH phase control bit is clear, data
is captured on the first clock edge transition. If the SPH bit is set, data is captured on the second
clock edge transition.
15.3.4.3
Freescale SPI Frame Format with SPO=0 and SPH=0
Single and continuous transmission signal sequences for Freescale SPI format with SPO=0 and
SPH=0 are shown in Figure 15-4 on page 950 and Figure 15-5 on page 950.
June 12, 2014
949
Texas Instruments-Production Data