TM4C1233H6PZ Datasheet, PDF (945/1243 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C1233H6PZ Microcontroller
reset. The exceptions to this rule are the SSI0Clk, SSI0Fss, SSI0Rx, and SSI0Tx pins, which
default to the SSI function. The "Pin Mux/Pin Assignment" column in the following table lists the
possible GPIO pin placements for the SSI signals. The AFSEL bit in the GPIO Alternate Function
Select (GPIOAFSEL) register (page 657) should be set to choose the SSI function. The number in
parentheses is the encoding that must be programmed into the PMCn field in the GPIO Port Control
(GPIOPCTL) register (page 675) to assign the SSI signal to the specified GPIO port pin. For more
information on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 632.
Table 15-1. SSI Signals (100LQFP)
Pin Name
Pin Number Pin Mux / Pin Pin Type Buffer Type^a Description
Assignment
SSI0Clk
28
PA2 (2)
I/O
TTL
SSI module 0 clock
SSI0Fss
29
PA3 (2)
I/O
TTL
SSI module 0 frame signal
SSI0Rx
30
PA4 (2)
I
TTL
SSI module 0 receive
SSI0Tx
31
PA5 (2)
O
TTL
SSI module 0 transmit
SSI1Clk
1
PD0 (2)
I/O
42
PF2 (2)
TTL
SSI module 1 clock.
SSI1Fss
2
PD1 (2)
I/O
43
PF3 (2)
TTL
SSI module 1 frame signal.
SSI1Rx
3
PD2 (2)
I
40
PF0 (2)
TTL
SSI module 1 receive.
SSI1Tx
4
PD3 (2)
O
41
PF1 (2)
TTL
SSI module 1 transmit.
SSI2Clk
79
PH4 (2)
I/O
92
PB4 (2)
TTL
SSI module 2 clock.
SSI2Fss
78
PH5 (2)
I/O
91
PB5 (2)
TTL
SSI module 2 frame signal.
SSI2Rx
77
PH6 (2)
I
TTL
SSI module 2 receive.
SSI2Tx
76
PH7 (2)
O
TTL
SSI module 2 transmit.
SSI3Clk
1
PD0 (1)
I/O
16
PH0 (2)
49
PK0 (2)
TTL
SSI module 3 clock.
SSI3Fss
2
PD1 (1)
I/O
17
PH1 (2)
48
PK1 (2)
TTL
SSI module 3 frame signal.
SSI3Rx
3
PD2 (1)
I
18
PH2 (2)
47
PK2 (2)
TTL
SSI module 3 receive.
SSI3Tx
4
PD3 (1)
O
19
PH3 (2)
46
PK3 (2)
TTL
SSI module 3 transmit.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
15.3
Functional Description
The SSI performs serial-to-parallel conversion on data received from a peripheral device. The CPU
accesses data, control, and status information. The transmit and receive paths are buffered with
internal FIFO memories allowing up to eight 16-bit values to be stored independently in both transmit
and receive modes. The SSI also supports the µDMA interface. The transmit and receive FIFOs
can be programmed as destination/source addresses in the µDMA module. µDMA operation is
enabled by setting the appropriate bit(s) in the SSIDMACTL register (see page 974).
June 12, 2014
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Texas Instruments-Production Data