TM4C1230H6PM Datasheet, PDF (941/1104 Pages) Texas Instruments – Tiva™ TM4C1230H6PM Microcontroller

Tiva^™ TM4C1230H6PM Microcontroller
Write-Only Control Register
I2C Master Control/Status (I2CMCS)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
Offset 0x004
Type WO, reset 0x0000.0020
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
HS
ACK STOP START RUN
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
WO
WO
WO
WO
WO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:5
4
Name
reserved
HS
Type
RO
WO
Reset
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
High-Speed Enable
Value Description
0 The master operates in Standard, Fast mode, or Fast mode
plus as selected by using a value in the I2CMTPR register that
results in an SCL frequency of 100 kbps for Standard mode,
400 kbps for Fast mode, or 1 Mpbs for Fast mode plus.
1 The master operates in High-Speed mode with transmission
speeds up to 3.33 Mbps.
3
ACK
WO
0
Data Acknowledge Enable
Value Description
0 The received data byte is not acknowledged automatically by
the master.
1 The received data byte is acknowledged automatically by the
master. See field decoding in Table 15-5 on page 942.
2
STOP
WO
0
Generate STOP
Value Description
0 The controller does not generate the STOP condition.
1 The controller generates the STOP condition. See field decoding
in Table 15-5 on page 942.
June 12, 2014
941
Texas Instruments-Production Data