TM4C1230H6PM Datasheet, PDF(873/1104 Page) Texas Instruments – Tiva™ TM4C1230H6PM Microcontroller

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TM4C1230H6PM Datasheet, PDF (873/1104 Pages) Texas Instruments – Tiva™ TM4C1230H6PM Microcontroller

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Tivaâ¢ TM4C1230H6PM Microcontroller

reset. The exceptions to this rule are the SSI0Clk, SSI0Fss, SSI0Rx, and SSI0Tx pins, which

default to the SSI function. The "Pin Mux/Pin Assignment" column in the following table lists the

possible GPIO pin placements for the SSI signals. The AFSEL bit in the GPIO Alternate Function

Select (GPIOAFSEL) register (page 593) should be set to choose the SSI function. The number in

parentheses is the encoding that must be programmed into the PMCn field in the GPIO Port Control

(GPIOPCTL) register (page 610) to assign the SSI signal to the specified GPIO port pin. For more

information on configuring GPIOs, see âGeneral-Purpose Input/Outputs (GPIOs)â on page 571.

Table 14-1. SSI Signals (64LQFP)

Pin Name

Pin Number Pin Mux / Pin Pin Type Buffer Typea Description

Assignment

SSI0Clk

19

PA2 (2)

I/O

TTL

SSI module 0 clock

SSI0Fss

20

PA3 (2)

I/O

TTL

SSI module 0 frame signal

SSI0Rx

21

PA4 (2)

I

TTL

SSI module 0 receive

SSI0Tx

22

PA5 (2)

O

TTL

SSI module 0 transmit

SSI1Clk

30

PF2 (2)

I/O

61

PD0 (2)

TTL

SSI module 1 clock.

SSI1Fss

31

PF3 (2)

I/O

62

PD1 (2)

TTL

SSI module 1 frame signal.

SSI1Rx

28

PF0 (2)

I

63

PD2 (2)

TTL

SSI module 1 receive.

SSI1Tx

29

PF1 (2)

O

64

PD3 (2)

TTL

SSI module 1 transmit.

SSI2Clk

58

PB4 (2)

I/O

TTL

SSI module 2 clock.

SSI2Fss

57

PB5 (2)

I/O

TTL

SSI module 2 frame signal.

SSI2Rx

1

PB6 (2)

I

TTL

SSI module 2 receive.

SSI2Tx

4

PB7 (2)

O

TTL

SSI module 2 transmit.

SSI3Clk

61

PD0 (1)

I/O

TTL

SSI module 3 clock.

SSI3Fss

62

PD1 (1)

I/O

TTL

SSI module 3 frame signal.

SSI3Rx

63

PD2 (1)

I

TTL

SSI module 3 receive.

SSI3Tx

64

PD3 (1)

O

TTL

SSI module 3 transmit.

a. The TTL designation indicates the pin has TTL-compatible voltage levels.

14.3

Functional Description

The SSI performs serial-to-parallel conversion on data received from a peripheral device. The CPU

accesses data, control, and status information. The transmit and receive paths are buffered with

internal FIFO memories allowing up to eight 16-bit values to be stored independently in both transmit

and receive modes. The SSI also supports the ÂµDMA interface. The transmit and receive FIFOs

can be programmed as destination/source addresses in the ÂµDMA module. ÂµDMA operation is

enabled by setting the appropriate bit(s) in the SSIDMACTL register (see page 902).

14.3.1

Bit Rate Generation

The SSI includes a programmable bit rate clock divider and prescaler to generate the serial output

clock. Bit rates are supported to 2 MHz and higher, although maximum bit rate is determined by

peripheral devices.

The serial bit rate is derived by dividing down the input clock (SysClk). The clock is first divided by

an even prescale value CPSDVSR from 2 to 254, which is programmed in the SSI Clock Prescale

June 12, 2014

873

Texas Instruments-Production Data

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