TMS320C6713B_15 Datasheet, PDF (93/154 Pages) Texas Instruments – FLOATING-POINT DIGITAL SIGNAL PROCESSOR

TMS320C6713B
FLOATINGĆPOINT DIGITAL SIGNAL PROCESSOR
SPRS294B − OCTOBER 2005 − REVISED JUNE 2006
the GIE bit in the CSR and the NMIE bit in the interrupt enable register (IER) must also be set in order for the
interrupt service routine to execute; otherwise, execution returns to the instruction where PD1 took effect upon
PD1 mode termination by an enabled interrupt.
PD2 and PD3 modes can only be aborted by device reset. Table 44 summarizes all the power-down modes.
Table 44. Characteristics of the Power-Down Modes
PRWD FIELD
(BITS 15−10)
000000
001001
010001
011010
011100
POWER-DOWN
MODE
No power-down
PD1
PD1
PD2†
PD3†
WAKE-UP METHOD
—
Wake by an enabled interrupt
Wake by an enabled or
non-enabled interrupt
Wake by a device reset
Wake by a device reset
EFFECT ON CHIP’S OPERATION
—
CPU halted (except for the interrupt logic)
Power-down mode blocks the internal clock inputs at the
boundary of the CPU, preventing most of the CPU’s logic from
switching. During PD1, EDMA transactions can proceed
between peripherals and internal memory.
Output clock from PLL is halted, stopping the internal clock
structure from switching and resulting in the entire chip being
halted. All register and internal RAM contents are preserved. All
functional I/O “freeze” in the last state when the PLL clock is
turned off.
Input clock to the PLL stops generating clocks. All register and
internal RAM contents are preserved. All functional I/O freeze in
the last state when the PLL clock is turned off. Following reset, the
PLL needs time to re−lock, just as it does following power−up.
Wake−up from PD3 takes longer than wake−up from PD2
because the PLL needs to be re−locked, just as it does following
power−up.
It is recommended to use the PLLPWDN bit (PLLCSR.1) as an
alternative to PD3.
All others
Reserved
—
—
† _{When entering PD2 and PD3, all functional I/O remains in the previous state. However, for peripherals which are asynchronous in nature or}
peripherals with an external clock source, output signals may transition in response to stimulus on the inputs. Under these conditions,
peripherals will not operate according to specifications.
power-supply sequencing
TI DSPs do not require specific power sequencing between the core supply and the I/O supply. However,
systems should be designed to ensure that neither supply is powered up for extended periods of time
(>1 second) if the other supply is below the proper operating voltage.
system-level design considerations
System-level design considerations, such as bus contention, may require supply sequencing to be
implemented. In this case, the core supply should be powered up prior to (and powered down after), the I/O
buffers. This is to ensure that the I/O buffers receive valid inputs from the core before the output buffers are
powered up, thus, preventing bus contention with other chips on the board.
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