TMS320C6713B_15 Datasheet, PDF (129/154 Pages) Texas Instruments – FLOATING-POINT DIGITAL SIGNAL PROCESSOR

TMS320C6713B
FLOATINGĆPOINT DIGITAL SIGNAL PROCESSOR
SPRS294B − OCTOBER 2005 − REVISED JUNE 2006
HOST-PORT INTERFACE TIMING
timing requirements for host-port interface cycles^†‡ (see Figure 55, Figure 56, Figure 57, and
Figure 58)
NO.
1 tsu(SELV-HSTBL) Setup time, select signals§ valid before HSTROBE low
2 th(HSTBL-SELV) Hold time, select signals§ valid after HSTROBE low
3 tw(HSTBL)
Pulse duration, HSTROBE low (host read access)
Pulse duration, HSTROBE low (host write access)
4 tw(HSTBH)
Pulse duration, HSTROBE high between consecutive accesses
10 tsu(SELV-HASL) Setup time, select signals§ valid before HAS low
11 th(HASL-SELV) Hold time, select signals§ valid after HAS low
12 tsu(HDV-HSTBH) Setup time, host data valid before HSTROBE high
13 th(HSTBH-HDV) Hold time, host data valid after HSTROBE high
Hold time, HSTROBE low after HRDY low. HSTROBE should not be inactivated
14 th(HRDYL-HSTBL) _{until HRDY is active (low); otherwise, HPI writes will not complete properly.}
PYP-200,-225
GDP/ZDP -225, -300
PYPA -167, -200
GDPA/ZDPA −200
MIN MAX
5
4
4P
4P
4P
5
3
5
3
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
2
ns
18 tsu(HASL-HSTBL) Setup time, HAS low before HSTROBE low
2
ns
19 th(HSTBL-HASL) Hold time, HAS low after HSTROBE low
2
ns
† _{HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.}
‡ _{P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.}
§ _{Select signals include: HCNTL[1:0], HR/W, and HHWIL.}
switching characteristics over recommended operating conditions during host-port interface
cycles^†‡ (see Figure 55, Figure 56, Figure 57, and Figure 58)
PYP-200,-225
GDP/ZDP -225, -300
NO.
PARAMETER
PYPA -167, -200 _UNIT
GDPA/ZDPA −200
5 td(HCS-HRDY) Delay time, HCS to HRDY¶
6 td(HSTBL-HRDYH) Delay time, HSTROBE low to HRDY high#
MIN MAX
1
12 ns
3
12 ns
7 td(HSTBL-HDLZ) Delay time, HSTROBE low to HD low impedance for an HPI read
2
ns
8 td(HDV-HRDYL) Delay time, HD valid to HRDY low
9 toh(HSTBH-HDV) Output hold time, HD valid after HSTROBE high
15 td(HSTBH-HDHZ) Delay time, HSTROBE high to HD high impedance
2P − 4
3
3
ns
12 ns
12 ns
16 td(HSTBL-HDV) Delay time, HSTROBE low to HD valid
3 12.5 ns
17 td(HSTBH-HRDYH) Delay time, HSTROBE high to HRDY high||
3
12 ns
† _{HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.}
‡ _{P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.}
¶ _{HCS enables HRDY, and HRDY is always low when HCS is high. The case where HRDY goes high when HCS falls indicates that HPI is busy}
completing a previous HPID write or READ with autoincrement.
# _{This parameter is used during an HPID read. At the beginning of the first half-word transfer on the falling edge of HSTROBE, the HPI sends the}
request to the EDMA internal address generation hardware, and HRDY remains high until the EDMA internal address generation hardware loads
the requested data into HPID.
|| _{This parameter is used after the second half-word of an HPID write or autoincrement read. HRDY remains low if the access is not an HPID write}
or autoincrement read. Reading or writing to HPIC or HPIA does not affect the HRDY signal.
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