TMS320C6713B_15 Datasheet, PDF (139/154 Pages) Texas Instruments – FLOATING-POINT DIGITAL SIGNAL PROCESSOR

TMS320C6713B
FLOATINGĆPOINT DIGITAL SIGNAL PROCESSOR
SPRS294B − OCTOBER 2005 − REVISED JUNE 2006
switching characteristics over recommended operating conditions for McBSP as SPI master or
slave: CLKSTP = 10b, CLKXP = 1^†‡ (see Figure 63)
NO.
PARAMETER
1 th(CKXH-FXL) Hold time, FSX low after CLKX high¶
2 td(FXL-CKXL) Delay time, FSX low to CLKX low#
3 td(CKXL-DXV) Delay time, CLKX low to DX valid
Disable time, DX high impedance following last data bit from
6 tdis(CKXH-DXHZ) _{CLKX high}
PYP-200,-225
GDP/ZDP -225, -300
PYPA -167, -200
GDPA/ZDPA −200
MASTER§
SLAVE
MIN MAX
MIN
MAX
T−2 T+3
H−2 H+3
−3
4 6P + 2 10P + 17
UNIT
ns
ns
ns
H−2 H+3
ns
7
tdis(FXH-DXHZ)
Disable time, DX high impedance following last data bit from
FSX high
2P + 3 6P + 17 ns
8 td(FXL-DXV)
Delay time, FSX low to DX valid
4P + 2 8P + 17 ns
† _{P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.}
‡ _{For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.}
§ _{S = Sample rate generator input clock = 2P if CLKSM = 1 (P = 1/CPU clock frequency)}
= Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
¶ _{FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX}
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
# _{FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock}
(CLKX).
CLKX
FSX
DX
DR
1
2
7
6
Bit 0
Bit 0
8
4
Bit(n-1)
Bit(n-1)
3
(n-2)
5
(n-2)
(n-3)
(n-3)
(n-4)
(n-4)
Figure 63. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
139