LM3S1F11 Datasheet, PDF (927/955 Pages) Texas Instruments – Stellaris® LM3S1F11 Microcontroller

Stellaris^® LM3S1F11 Microcontroller
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Micro Direct Memory Access (μDMA)
μDMA Registers (Offset from μDMA Base Address)
Base 0x400F.F000
DMASTAT, type RO, offset 0x000, reset 0x001F.0000
STATE
DMACHANS
MASTEN
DMACFG, type WO, offset 0x004, reset -
DMACTLBASE, type R/W, offset 0x008, reset 0x0000.0000
ADDR
DMAALTBASE, type RO, offset 0x00C, reset 0x0000.0200
DMAWAITSTAT, type RO, offset 0x010, reset 0xFFFF.FFC0
DMASWREQ, type WO, offset 0x014, reset -
DMAUSEBURSTSET, type R/W, offset 0x018, reset 0x0000.0000
DMAUSEBURSTCLR, type WO, offset 0x01C, reset -
DMAREQMASKSET, type R/W, offset 0x020, reset 0x0000.0000
DMAREQMASKCLR, type WO, offset 0x024, reset -
DMAENASET, type R/W, offset 0x028, reset 0x0000.0000
DMAENACLR, type WO, offset 0x02C, reset -
DMAALTSET, type R/W, offset 0x030, reset 0x0000.0000
DMAALTCLR, type WO, offset 0x034, reset -
DMAPRIOSET, type R/W, offset 0x038, reset 0x0000.0000
DMAPRIOCLR, type WO, offset 0x03C, reset -
ADDR
ADDR
ADDR
WAITREQ[n]
WAITREQ[n]
SWREQ[n]
SWREQ[n]
SET[n]
SET[n]
CLR[n]
CLR[n]
SET[n]
SET[n]
CLR[n]
CLR[n]
SET[n]
SET[n]
CLR[n]
CLR[n]
SET[n]
SET[n]
CLR[n]
CLR[n]
SET[n]
SET[n]
CLR[n]
CLR[n]
MASTEN
January 23, 2012
927
Texas Instruments-Production Data