LM3S1F11 Datasheet, PDF (524/955 Pages) Texas Instruments – Stellaris® LM3S1F11 Microcontroller

External Peripheral Interface (EPI)
Register 29: EPI Interrupt Mask (EPIIM), offset 0x210
This register is the interrupt mask set or clear register. For each interrupt source (read, write, and
error), a mask value of 1 allows the interrupt source to trigger an interrupt to the interrupt controller;
a mask value of 0 prevents the interrupt source from triggering an interrupt.
Note that interrupt masking has no effect on μDMA, which operates off the raw source of the read
and write interrupts.
EPI Interrupt Mask (EPIIM)
Base 0x400D.0000
Offset 0x210
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
WRIM RDIM ERRIM
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:3
2
Name
reserved
WRIM
Type
RO
R/W
Reset
0x000
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Write FIFO Empty Interrupt Mask
Value Description
0 WRRIS in the EPIRIS register is masked and does not cause
an interrupt.
1 WRRIS in the EPIRIS register is not masked and can trigger an
interrupt to the interrupt controller.
1
RDIM
R/W
0
Read FIFO Full Interrupt Mask
Value Description
0 RDRIS in the EPIRIS register is masked and does not cause
an interrupt.
1 RDRIS in the EPIRIS register is not masked and can trigger an
interrupt to the interrupt controller.
0
ERRIM
R/W
0
Error Interrupt Mask
Value Description
0 ERRIS in the EPIRIS register is masked and does not cause
an interrupt.
1 ERRIS in the EPIRIS register is not masked and can trigger an
interrupt to the interrupt controller.
524
January 23, 2012
Texas Instruments-Production Data